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Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 TM Microprocessor
BibTeX
@MISC{_floatingpoint,
author = {},
title = {Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 TM Microprocessor},
year = {}
}
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Abstract
This paper presents the AMD-K7 IEEE 754 and x87 compliant floating point division and square root algorithms and implementation. The AMD-K7 processor employs an iterative implementation of a series expansion to converge quadratically to the quotient and square root. Highly accurate initial approximations and a high performance shared floating point multiplier assist in achieving low division and square root latencies at high operating frequencies. A novel time-sharing technique allows independent floating point multiplication operations to proceed while division or square root computation is in progress. Exact IEEE 754 rounding for all rounding modes and target precisions has been verified by conventional directed and random testing procedures, along with the formulation of a mechanically-checked formal proof using the ACL2 theorem prover. 1
Keyphrases
point division square root algorithm amd-k7 tm microprocessor series expansion square root latency point multiplication operation random testing procedure point multiplier amd-k7 processor amd-k7 ieee acl2 theorem prover square root computation square root highly accurate initial approximation high performance low division novel time-sharing technique exact ieee iterative implementation mechanically-checked formal proof target precision
