BibTeX
@MISC{Chen_arithmeticcircuit,
author = {Yirng-an Chen},
title = {Arithmetic Circuit Verification Based onWord-Level Decision Diagrams},
year = {}
}
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Abstract
i Abstract The division bug in Intel's Pentium processor has demonstrated the importance and the difficultyof verifying arithmetic circuits and the high cost of an arithmetic bug. In this thesis, we develop verification methodologies and symbolic representations for functions mapping Boolean vectorsto integer or floating-point values, and build verification systems for arithmetic circuits. Our first approach is based on a hierarchical methodology and uses multiplicative binarymoment diagrams (*BMDs) to represent functions symbolically for verification of integer circuits. *BMDs are particularly effective for representing and manipulating functions mappingBoolean vectors to integer values. Our hierarchical methodology exploits the modular structure of arithmetic circuits to speed up the verification task. Based on this approach, we have verifieda wide range of integer circuits such as multipliers and dividers.
Keyphrases
arithmetic circuit arithmetic circuit verification onword-level decision diagram hierarchical methodology integer circuit boolean vectorsto integer verification task floating-point value build verification system pentium processor arithmetic bug division bug first approach symbolic representation wide range multiplicative binarymoment diagram modular structure verification methodology high cost function mappingboolean vector
