Enforcing Safety of Real-Time Schedules on Contemporary Processors using a Virtual Simple Architecture (VISA

Enforcing Safety of Real-Time Schedules on Contemporary Processors using a Virtual Simple Architecture (VISA (2004)

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by Aravindh Anantaraman , Kiran Seth , Eric Rotenberg , Frank Mueller

Venue:	In Proceedings of the IEEE Real-Time Systems Symposium
Citations:	11 - 5 self

BibTeX

@INPROCEEDINGS{Anantaraman04enforcingsafety,
    author = {Aravindh Anantaraman and Kiran Seth and Eric Rotenberg and Frank Mueller},
    title = {Enforcing Safety of Real-Time Schedules on Contemporary Processors using a Virtual Simple Architecture (VISA},
    booktitle = {In Proceedings of the IEEE Real-Time Systems Symposium},
    year = {2004},
    pages = {114--125}
}

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Abstract

Determining safe and tight upper bounds on the worst-case execution time (WCET) of hard real-time tasks running on contemporary microarchitectures is a difficult problem. Current trends in microarchitecture design have created a complexity wall: By enhancing performance through ever more complex architectural features, systems have become increasingly hard to analyze. This paper extends a framework, introduced previously as Virtual Simple Architecture (VISA), to multi-tasking real-time systems. The objective of VISA is to obviate the need to statically analyze complex processors by instead shifting the burden of guaranteeing deadlines – in part – onto the hardware. The VISA framework exploits a complex processor that ordinarily operates with all of its advanced features enabled, called the complex mode, but which can also be downgraded to a simple mode by gating off the advanced

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