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FRAIGs: A unifying representation for logic synthesis and verification (2005)
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@TECHREPORT{Mishchenko05fraigs:a,
author = {Alan Mishchenko and Satrajit Chatterjee and Robert Brayton},
title = {FRAIGs: A unifying representation for logic synthesis and verification},
institution = {},
year = {2005}
}
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Abstract
AND-INV graphs (AIGs) are Boolean networks composed of twoinput AND-gates and inverters. In the known applications, such as equivalence checking and technology mapping, AIGs are used to represent and manipulate Boolean functions. AIGs powered by simulation and Boolean satisfiability lead to functionally reduced AIGs (FRAIGs), which are “semi-canonical ” in the sense that each FRAIG node has unique functionality among all the nodes currently present in the FRAIG. The paper shows that FRAIGs can be used to unify and enhance many phases of logic synthesis: from the representation of the original and the intermediate netlists derived by logic optimization, through technology mapping over multiple logic structures, to combinational equivalence checking. Experimental results on large public benchmarks confirm the practicality of using FRAIGs throughout the logic synthesis flow. 1
Keyphrases
logic synthesis unifying representation technology mapping intermediate netlists many phase boolean network logic optimization and-inv graph fraig node twoinput and-gates boolean satisfiability lead logic synthesis flow equivalence checking combinational equivalence checking known application boolean function experimental result large public benchmark unique functionality multiple logic structure
