A novel low-power FPGA routing switch

A novel low-power FPGA routing switch (2004)

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by Jason H. Anderson , Farid N. Najm

Venue:	IEEE Custom Integrated Circuits Conference
Citations:	7 - 2 self

BibTeX

@INPROCEEDINGS{Anderson04anovel,
    author = {Jason H. Anderson and Farid N. Najm},
    title = {A novel low-power FPGA routing switch},
    booktitle = {IEEE Custom Integrated Circuits Conference},
    year = {2004},
    pages = {719--722}
}

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Abstract

We propose a new programmable FPGA routing switch that can operate in three different modes: high-speed, low-power or sleep. High-speed mode offers similar power and performance to a traditional routing switch. In low-power mode, power is reduced at the expense of speed. Leakage power is reduced by 36-40 % in low-power vs. high-speed mode (on average); dynamic power is reduced by up to 28%. Leakage power in sleep mode is 61 % lower than in high-speed mode. The applicability of the new switch is motivated through an analysis of timing slack in industrial FPGA designs. Specifically, we show that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance. I.

Citations

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49	Architecture evaluation for powerefficient FPGAs - Li, Chen, et al.
32	Dynamic power consumption in Virtex-II FPGA family - Shang, Kaviani, et al.
31	Leakage power analysis of a 90nm FPGA - Tuan, Lai - 2002
31	Low-power FPGA using Pre-Defined Dual-Vdd/Dual-Vt Fabrics - Li, Lin, et al. - 2004
28	Design Methodology for Fine-grained Leakage Control in MTCMOS - Calhoun, Honore, et al. - 2003
26	Design of Interconnection Networks for Programmable Logic - Lemieux, Lewis - 2004
23	Dynamic and Leakage Power Reduction in MTCMOS Circuits using an Automated Efficient Gate Clustering Technique - Anis, Areibi, et al.
15	Low-Energy FPGAs: Architecture and Design - George, Rabaey - 2001
13	Evaluation of Low-Leakage Design Techniques for Field Programmable Gate Arrays - Rahman, Polavarapuv - 2004
13	Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits - Wang, Vrudhula - 2002
11	A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations - Kim, Kim, et al. - 2005
8	High-performance and low-power challenges for sub-70nm microprocessor circuits - Krishnamurthy, Alvandpour, et al. - 2002
7	An Asymmetric SRAM cell to lower gate leakage - Azizi, Najm
5	A novel powering-down scheme for low Vt CMOS circuits - Kumagai, Iwaki, et al. - 1998