A 0.9 V 9 mW 1 MSPS digitally calibrated ADC with 75 dB (2003)
| Venue: | SFDR,” IEEE VLSI Circuits Symp |
| Citations: | 7 - 6 self |
BibTeX
@INPROCEEDINGS{Chang03a0.9,
author = {Dong-young Chang and Gil-cho Ahn and Un-ku Moon},
title = {A 0.9 V 9 mW 1 MSPS digitally calibrated ADC with 75 dB},
booktitle = {SFDR,” IEEE VLSI Circuits Symp},
year = {2003},
pages = {67--70},
publisher = {Inc}
}
Bookmark
 |
 |
 |
 |
 |
 |
OpenURL
Abstract
A low-voltage two-stage algorithmic ADC incorporating the Opamp-Reset Switching Technique (ORST) is presented. The low-voltage digital CMOS process compatible operation is achieved without the clock boosting/bootstrapping or switched-opamp. The ADC employs a highly linear input sampling circuit at the front-end, and the digital output is calibrated using a radix-based scheme. The prototype was fabricated in a 0.18-µm CMOS technology and the active die area is 1.2mm × 1.2mm. The calibrated ADC demonstrates 75dB SFDR at 0.9V and 80dB SFDR at 1.2V. The total power consumption of the ADC is 9mW at the clock frequency of 7MHz (1MSPS). Keywords: Low-voltage, opamp-reset switching technique, pipeline ADC, input sampling circuit, radix-based digital calibration.
Citations
| 37 | A 15-b 1-MSample/s digitally self-calibrated pipeline ADC - Karanicolas, Lee, et al. - 1993 |
| 21 | A 12-b digital-background calibrated algorithmic ADC with 090 dB THD - Erdogan, Hurst, et al. - 1999 |
| 9 | Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs - Chang, li, et al. - 2004 |
| 2 | Low-voltage pipelined ADC using opamp-reset switching technique - Chang, Wu, et al. - 2002 |
| 2 | et al., “A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipelined A/D converter - Matsuura - 1998 |
| 1 | 1-V input sampling circuit for multi-stage ADC - Chang, Moon |
