DMCA
A Unified Processor Architecture for RISC & VLIW DSP
BibTeX
@MISC{Lin_aunified,
author = {Tay-jyi Lin and Chie-min Chao and Chia-hsien Liu and Pi-chen Hsiao and Shin-kai Chen and Li-chun Lin and Chih-wei Liu and Chein-wei Jen},
title = {A Unified Processor Architecture for RISC & VLIW DSP},
year = {}
}
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Abstract
This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mm ×3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.
Keyphrases
unified processor architecture risc vliw dsp dsp mode operation mode compiler-friendly mips-like core processor core risc mode ping-pong register organization single program stream cmos technology hierarchical instruction encoding data manipulation risc instruction average power 4-way vliw dsp datapath program flow on-chip memory core size control construct stream processing vliw code unified processor core
