Abstract

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

Citations

2801	Optimization by simulated annealing - Kirkpatrick, Gelatt, et al. - 1983
2605	Graph-based algorithms for Boolean function manipulation - Bryant - 1986
864	An Efficient Heuristic Procedure for Partitioning Graphs - Kernighan, Lin - 1970
382	Circuits, interconnections and packaging for VLSI - Bakoglu - 1990
320	Logic Minimization Algorithms For VLSI Synthesis - Brayton, McMullen, et al. - 1984
279	Power analysis of embedded software: A first step towards software power minimization - Tiwari, Malik, et al. - 1994
159	Gordian: VLSI placement by quadratic programming and slicing optimization - Kleinhans, Sigl, et al. - 1991
140	Short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits - Veendrick - 1984
127	Transition Density: A New Measure of Activity in Digital Circuits - Najm - 1993
122	Low Power Design Methodologies - Rabaey, Pedram - 1996
108	Optimizing synchronous circuitry by retiming - Leiserson, Rose, et al. - 1993
103	Multilevel logic synthesis - Brayton, Hachtel, et al.
95	Packaging for VLSI - Bakoglu, Circuits - 1990
88	Precomputation-Based Sequential Logic Optimization for Low Power - Alidina, Monteiro, et al. - 1994
86	Probabilistic Treatment of General Combinational Networks - Parker, McCluskey - 1975
84	A Monte Carlo approach for power estimation - Burch, Najm, et al. - 1993
82	Estimation of average switching activity in combinational and sequential circuits - GHOSH, DEVADAS, et al. - 1992
82	Global communication and memory optimizing transformations for low power signal processing systems - Catthoor, Franssen, et al. - 1994
78	Towards a high-level power estimation capability - Nemani, Najm - 1996
76	On average power dissipation and random pattern testability of CMOS combinational logic networks - Shen, Ghosh, et al. - 1992
71	CMOS circuit speed and buffer optimization - Hedenstierna, Jeppson - 1987
71	NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementation - Villa, Sangiovanni-Vincentelli - 1990
63	Retiming Sequential Circuits for Low Power - Monteiro, Devadas, et al. - 1993
61	Variable voltage scheduling - Raje, Sarrafzadeh - 1995
59	Low-Power Digital Design - Horowitz, Indermaur, et al. - 1994
59	Activity-sensitive architectural power analysis - Landman, Rabaey - 1996
59	Probabilistic simulation for reliability analysis - Najm, Burch, et al. - 1990
59	Technology Decomposition and Mapping Targeting Low Power - Tsui, Pedram, et al.
57	Bus-invert coding for low power I/O - Stan, Burleson - 1995
54	Behavioral level power estimation and exploration - Mehra, Rabaey - 1994
52	Low power digital systems based on adiabatic switching principles”,IEEE transactions on VLSI systems, V-2, Issue-4, Dec-1994. [8]. Sk.NoorMahammad and KamakotiVeezhinathan, “Constructing Online Testable Circuits Using Reversible - Athas - 1801
52	Behavioral synthesis for low power - RAGHUNATHAN, K - 1994
52	IRSIM: an incremental MOS switch-level simulator - Salz, Horowitz - 1989
51	Low-power operation using self-timed circuits and adaptive scaling of the supply voltage - Nielsen, Niessen, et al. - 1994
51	Low power architecture design and compilation techniques for high-performance processors - Su, Tsui - 1994
49	HYPER-LP: A system for power minimization using architectural transformations - Potkonjak, Rabaey, et al. - 1992
49	Simultaneous driver and wire sizing for performance and power optimization - Cong, Koh - 1994
48	Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation - Devadas, Keutzer, et al. - 1992
48	Accurate simulation of power dissipation in VLSI circuits,” in - Kang - 1986
47	Batteries for low power electronics - POWERS - 1995
46	Efficient Power estimation for highly correlated input streams - Marculescu, Marculescu, et al. - 1995
46	Technology mapping for low power - Tiwari, Ashar, et al. - 1993
45	Exact and approximate methods for calculating signal and transition probabilities in FSMs - Tsui, Pedram, et al. - 1994
43	Power Estimation for High Level Synthesis - Landman, Rabaey
43	The testability-preserving concurrent decomposition and factorization of Boolean expressions - Rajski, Vasudevamurthy
43	Statistical estimation of the switching activity in digital circuits - Xakellis, Najm - 1994
42	Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design - Tiwari, Malik, et al. - 1998
40	Trends in low-power RAM circuit technologies - Itoh, Sasaki, et al. - 1995
40	Information theoretic measures for energy consumption at the register-transfer level - Marculescu, Marculescu, et al. - 1995
40	An exact zero-skew clock routing algorithm - Tsay - 1993