## TEMPLATE: A generic TEchnology Mapping PLATform (1997)

Venue: | IN PREPARATION, PREPRINT-REIHE, INSTITUT F"UR INFORMATIK, UNIVERSIT"AT W"URZBURG |

Citations: | 8 - 2 self |

### BibTeX

@TECHREPORT{Hinsberger97template:a,

author = {Uwe Hinsberger and Reiner Kolla},

title = {TEMPLATE: A generic TEchnology Mapping PLATform},

institution = {IN PREPARATION, PREPRINT-REIHE, INSTITUT F"UR INFORMATIK, UNIVERSIT"AT W"URZBURG},

year = {1997}

}

### OpenURL

### Abstract

Technology mapping problems arize in logic synthesis systems, when the gap between a synthesized boolean network and the implementation of that network within a given target technology has to be bridged. This paper presents a modular, versatile technology mapping system that supports many different target technologies. Guided by a complexity analysis of the problem, we develop a variety of efficient, exact or heuristic methods for technology driven network clustering. Depending on the target technology and optimization methods and goals, different subnetworks must be provided as candidates for clustering. Methods to achieve this are also included. We conclude with experimental results we obtained with several configurations of the system for different target technologies.

### Citations

278 | Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
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(Show Context)
Citation Context ...king) looks for two successive lookup tables that can be merged together; in order to accomplish a maximal number of these operations simultaneously, a matching-based algorithm is applied. In FlowMap =-=[6]-=- a labeling procedure is presented that is depth-optimal even for general acyclic networks. This procedure considers all nodes in topological order and solves a min-cut problem for each node; if there... |

275 | Synthesis and Optimization Benchmarks User Guide”, 2002, Available: ftp://mcnc.mcnc.org
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(Show Context)
Citation Context ...onical representative has been proven very effective. An important point was also, to compute the NPN-equivalence classes for all cell configurations. The small lib2 library of the MCNC benchmark set =-=[43]-=- contains 27 cells and can realize only 13 equivalence classes. By using configurations of cells, we could increase the number of NPN-equivalence classes to 30; in particular all two-dimensional and 7... |

66 | Y.: On Area/Depth Trade-Off in LUT-Based FPGA Technology Mapping - Cong, Ding - 1994 |

62 | Chortle-crf: Fast Technology Mapping for Lookup Tabled-Based FPGAs
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(Show Context)
Citation Context ... fanout-free regions and uses a dynamic program to realize each region with a minimal number of lookup tables. For decomposition of nodes with large fan in an exhaustive approach is used. Chortle-crf =-=[11]-=- repairs the main drawbacks of Chortle: now a much more efficient bin packing heuristic is used for the decomposition of big nodes. Furthermore reconvergent paths and duplication of logic at fanout no... |

54 |
DAG-Map: graph-based FPGA technology mapping for delay optimization
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(Show Context)
Citation Context ...FPGA [24] uses a genetic algorithm for solving the problem. Several methods very similar to the ideas we use for general technologies were developed independently by Cong et.al. for FPGAs. In DAG-Map =-=[4]-=- they minimize the depth and consider area as a secondary objective: during a preprocessing pass, the multi-input gates are decomposed into 2-input gates, such that the depth of the resulting network ... |

54 |
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(Show Context)
Citation Context ...of the question, because the pattern set would be huge. Especially technology mapping for FPGAs has been investigated intensively. The first technology mapper for lookup table-based FPGAs was Chortle =-=[10]-=-, which partitions the given network into its fanout-free regions and uses a dynamic program to realize each region with a minimal number of lookup tables. For decomposition of nodes with large fan in... |

54 |
BDD-based Decomposition of Logic Functions with Application to FPGA Synthesis
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(Show Context)
Citation Context ...decompositions and use a cover representation of the onset and offset of the function. At first, this representation also has been used by MIS and has been speeded-up significantly by the use of BDDs =-=[26]-=-. This paper also generalizes to non-disjoint decompositions and to incompletely specified functions. More recent work takes a look at several aspects of Roth-Karp decomposition, which have been tackl... |

51 |
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Citation Context ... FPGAs depth minimization [6] and duplication-free area minimization [5, 7] can be done in polynomial time. These observations seem to contradict the often cited complexity results about DAG-covering =-=[3, 1]-=- --- or to imply P = NP . However, the reductions used within these papers about code generation are not based on finding an optimal clustering of a DAG, but on minimizing the number of load/store ins... |

48 |
Performance-Oriented Technology Mapping
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(Show Context)
Citation Context ... cells, that cannot be represented as trees, e.g. multiplexer and 2 XOR, can be used. However DAG-covering is done heuristically: people thought all kinds of DAG-covering to be NP-complete. Therefore =-=[41]-=- returned to tree-covering, but their approach is not restricted to just one cost measure: they are able to minimize area under a delay constraint. After these fundamental proposals for general librar... |

45 |
Technology Mapping of Lookup Table-Based FPGAs for Performance
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(Show Context)
Citation Context ...hortle: now a much more efficient bin packing heuristic is used for the decomposition of big nodes. Furthermore reconvergent paths and duplication of logic at fanout nodes can be exploited. Chortle-d =-=[12]-=- uses a performance-oriented variant of this algorithm. Xmap [22] converts the network to an if-then-else DAG and performs an heuristical marking pass on this graph. GAFPGA [24] uses a genetic algorit... |

40 |
Module Clustering to Minimize delay in Digital networks
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(Show Context)
Citation Context ...al fan in and i the number of the primary inputs; this is done by means of an algorithm similar to Huffman's encoding procedure. The main pass performs module clustering, similar to Lawler's approach =-=[27]-=-. At first, the network is traversed in topological order and each node is labeled with its level in the final solution; then a backward traversal substitutes subgraphs by lookup tables. The labeling ... |

39 |
The Transduction Method - Design of Logic Networks Based on Permissible Functions
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(Show Context)
Citation Context ...om the candidate set. The input phases of candidates then determine the phases of the input nodes for cost computation. Last but not least, we can also take into account compatible local don't cares (=-=[35]-=-) in order to increase the candidate set. Let us first consider the problem, to match a sector function against a library of cell functions modulo NPN-equivalence. 23 Definition 8 Two functions f and ... |

37 | Xmap: A technology mapper table-lookup fieldProgrammable gate arrays
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(Show Context)
Citation Context ...or the decomposition of big nodes. Furthermore reconvergent paths and duplication of logic at fanout nodes can be exploited. Chortle-d [12] uses a performance-oriented variant of this algorithm. Xmap =-=[22]-=- converts the network to an if-then-else DAG and performs an heuristical marking pass on this graph. GAFPGA [24] uses a genetic algorithm for solving the problem. Several methods very similar to the i... |

37 |
Improved logic synthesis algorithms for table look up architectures
- Murgai, Shenoy, et al.
- 1991
(Show Context)
Citation Context ...tions ff 1 (X); : : : ; ff t (X) over the bound set X. Partition is based on kernel extraction, on AND-OR decomposition and on collapsing some nodes into their fanouts. An improved version of MIS-pga =-=[32]-=- integrated bin packing and new decomposition techniques. During technology-independent optimization a better cost estimate than the number of literals is used. Further improvements are achieved by us... |

34 |
Logic Synthesis for Programmable Gate Arrays
- Murgai, Nishizaki, et al.
- 1990
(Show Context)
Citation Context ...imization pass using the algorithm for the duplication-free case, predecessor packing and flow-pack. Whereas all these systems mainly concentrate on clustering of the given network structure, MIS-pga =-=[31]-=- follows the idea, that for FPGAs synthesis and technology mapping should be merged together as much as possible. The covering step, formulated as a binate covering problem, becomes a marginal postpro... |

33 |
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- Micheli
- 1994
(Show Context)
Citation Context ... to obtain compatible don't cares, i.e. don't cares which are valid independent from the choice of other don't cares for all other cell candidates, is to compute controllability don't cares (see e.g. =-=[8]-=-) only. In that case, the image computation method has proven superior for most benchmark circuits. A more complex option is a generalization of Murogas [35] method to compute maximum sets of compatib... |

32 |
Code generation for a one-register machine
- BRUNO, SETHI
- 1976
(Show Context)
Citation Context ... FPGAs depth minimization [6] and duplication-free area minimization [5, 7] can be done in polynomial time. These observations seem to contradict the often cited complexity results about DAG-covering =-=[3, 1]-=- --- or to imply P = NP . However, the reductions used within these papers about code generation are not based on finding an optimal clustering of a DAG, but on minimizing the number of load/store ins... |

29 |
Technology mapping in MIS
- Detjens, Ganot, et al.
- 1987
(Show Context)
Citation Context ... program to cover each region with tree-patterns representing the cells of the target technology. A postprocessing pass performs local optimizations at region boundaries. The technology mapper of MIS =-=[9]-=- improves this basic idea in several ways: It adds inverter pairs between adjacent gates, such that the de Morgan's law can be used during covering. Furthermore duplication of logic at fanouts can be ... |

29 |
Technology Mapping Using Boolean Matching and Don’t Care Sets
- Mailhot, Micheli
- 1990
(Show Context)
Citation Context ... 1 1 ; : : : ; x 'n n ) is a phase assignment. (x 0 i := x i ; x 1 i := x i ) There are several approaches treating the problem, how f ? jg can be decided without enumerating all triples ('; ; \Phi): =-=[28]-=- use symmetry and unateness for search space reduction. Don't cares can be considered by means of the so-called matching compatibility graph. [37] besides symmetry exploit the satisfy count of the cof... |

29 |
Functional multipleoutput decomposition: theory and an implicit algorithm
- Wurth, Eckl, et al.
- 1995
(Show Context)
Citation Context ...t with X = ; and Y , containing all variables; then they greedily select one variable after the other to be swapped from Y to X, such that the number of equivalence classes induced by X is minimized. =-=[42] give-=- a solution for multiple-output decomposition using common subfunctions. They demonstrate, that such decomposition functions can be constructed w.l.o.g. by taking into account the "global partiti... |

23 |
Permutation and Phase Independent Boolean Comparison
- Mohnke, Malik
- 1993
(Show Context)
Citation Context ...ploit the satisfy count of the cofactors. Cells belonging to the same NPN-equivalence class are stored together; thus a subcircuit's function has to be matched only against one element of each class. =-=[29]-=- use the satisfy count of additional subfunctions and refine these signatures for further reduction of the search space. However, these approaches leave the open question whether f can be matched agai... |

22 |
Optimal Technology Mapping for Single Output Cells
- Kolla
- 1994
(Show Context)
Citation Context ...generalization of our work about gate sizing [13, 14] to technology mapping and from the observation that certain DAG-covering problems, especially duplication-free mapping, can be solved efficiently =-=[15, 18]-=-. This observations harmonize well with the results of Cong and Ding who found out independently, that for FPGAs depth minimization [6] and duplication-free area minimization [5, 7] can be done in pol... |

22 |
Performance directed synthesis for table look up programmable gate arrays
- Murgai, Shenoy, et al.
- 1991
(Show Context)
Citation Context ...s used. Further improvements are achieved by using the exact cover algorithm locally and by extending partition. Moreover special techniques for two-output CLB's have been integrated. MIS-pga (delay) =-=[33]-=- consists of two phases, one for minimizing the depth and one for computing a fast placement, taking into account the wiring delays. The first phase is based on collapsing nodes into their fanouts, mo... |

21 | Optimum Functional Decomposition Using Encoding
- Murgai, Brayton, et al.
- 1994
(Show Context)
Citation Context ...s and to incompletely specified functions. More recent work takes a look at several aspects of Roth-Karp decomposition, which have been tackled by the original version of MIS-pga in an arbitrary way: =-=[34]-=- use multi-valued minimization and encoding techniques originating from FSM-synthesis for determining the decomposition functionssff 1 ; : : : ; ff t in such a way, that the composition function becom... |

17 |
Technology Binding and Local Optimization by DAG Matching
- DAGON
- 1987
(Show Context)
Citation Context ...ave to be realized by sequences of complex machine instructions. Therefore, the first technology mappers used tree-matching techniques originating from this domain. The core of the first system DAGON =-=[23]-=- even has been synthesized by means of a generator for code generators. DAGON partitions the boolean network into the forest of its fanout-free regions and uses a dynamic program to cover each region ... |

13 |
Boolean matching in logic synthesis
- Savoj, Silva, et al.
- 1992
(Show Context)
Citation Context ... decided without enumerating all triples ('; ; \Phi): [28] use symmetry and unateness for search space reduction. Don't cares can be considered by means of the so-called matching compatibility graph. =-=[37]-=- besides symmetry exploit the satisfy count of the cofactors. Cells belonging to the same NPN-equivalence class are stored together; thus a subcircuit's function has to be matched only against one ele... |

10 | Matching a Boolean Function against a Set of Functions
- Hinsberger, Kolla
- 1997
(Show Context)
Citation Context ... : ; g n g without matching f against each g i . This is important if there are many cells and/or in particular if the library L contains all functions that can be obtained by cell configurations. In =-=[16]-=- we developed methods to do this with a time complexity almost independent from the number of functions provided by the library. Since detailed presentation of these methods would be out of the scope ... |

9 | Approximative Representation of boolean Functions by size controllable ROBDD’s
- Kunjan, Hinsberger, et al.
- 1997
(Show Context)
Citation Context ...to achieve this, but even then the time and space requirement have been to large for bigger benchmark circuits. Therefore, we developed a method for approximative representation of boolean functions (=-=[17]-=-) by pairs of ROBDDs, that represent the function by a lower and upper bound. It is possible to develop reduction methods to control the sizes of these ROBDDs by decreasing the precision. Nevertheless... |

9 |
GAFAP: genetic algorithm for FPGA technology mapping
- Kommu, Pomenraz
- 1993
(Show Context)
Citation Context ...e exploited. Chortle-d [12] uses a performance-oriented variant of this algorithm. Xmap [22] converts the network to an if-then-else DAG and performs an heuristical marking pass on this graph. GAFPGA =-=[24]-=- uses a genetic algorithm for solving the problem. Several methods very similar to the ideas we use for general technologies were developed independently by Cong et.al. for FPGAs. In DAG-Map [4] they ... |

9 |
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
- Shen, Huang, et al.
- 1995
(Show Context)
Citation Context ...d performs a branch and bound algorithm for finding the best cut through the diagram; the cut computation algorithm works 1 t = 1 2 X " Y = ; 4 with an implicit representation of the set of all c=-=uts. [39]-=- tackle the same problem, using a cover representation of onset and offset. They start with X = ; and Y , containing all variables; then they greedily select one variable after the other to be swapped... |

8 |
On Area/Depth Trade-off
- Cong, Ding
- 1993
(Show Context)
Citation Context ...werful procedure flow-pack which is able to pack larger sets of lookup-tables; flow-pack also is based on the iterated computation of the maximum volume min-cut within an auxiliary network. FlowMap-r =-=[5, 7]-=- contains algorithms for optimal duplication-free area minimization and for computing area/depth tradeoffs. Duplication-free optimization is based on two observations concerning the so-called maximum ... |

8 |
A method for finding good Ashenhurst decompositions and its application to FPGA synthesis
- Stanion, Sechen
- 1995
(Show Context)
Citation Context ...ued minimization and encoding techniques originating from FSM-synthesis for determining the decomposition functionssff 1 ; : : : ; ff t in such a way, that the composition function becomes simple. In =-=[40]-=- an approach for computing a good partition of the variables without enumerating all partitions is presented. This approach uses a BDD representation for f , heuristically reorders the variables withi... |

6 |
Exploiting Communication Complexity for Multilevel Logic Synthesis
- Hwang, Owens, et al.
- 1990
(Show Context)
Citation Context ... general target technologies was almost forgotten. However, it has been shown that decomposition techniques similar to Roth-Karp decomposition also work well for other technologies: the system factor =-=[19, 20]-=- also partitions the variables into two disjoint sets X and Y and then decomposes the function f into three (multi-output) functions ~ f , f l and f r such that f(X; Y ) = ~ f (f l (X); f r (Y )). Usi... |

5 |
Efficient computing communication complexity for multilevel logic synthesis
- Hwang, Owens, et al.
- 1992
(Show Context)
Citation Context ...~ f , f l and f r which are decomposed recursively. Within each step, an optimal partition of the variables, i.e. a partition which minimizes the rank of D, is computed by exhaustive search. FactorII =-=[21]-=- significantly speeds-up this approach by using the Kernighan-Lin algorithm or a greedy approach for this task and by efficiently computing the communication complexity using a cube representation of ... |

5 | Communication Based Multilevel Synthesis for Multi-Output Boolean Functions
- Molitor, Scholl
- 1994
(Show Context)
Citation Context ...cation complexity using a cube representation of f and f instead of the decomposition chart. After a good partition is found, decomposition is done by factoring a collapsed decomposition chart. Mulop =-=[30]-=- works with an approach for the well-directed computation of decomposition functions common to different outputs: first, the outputs are divided heuristically into disjoint sets, such that the element... |

5 |
Area and delay mapping for table-look-up based field programmable gate arrays
- SAWKAR, THOMAS
- 1992
(Show Context)
Citation Context ...ble 5 compares realizations obtained with a TEMPLATE configuration for depth optimization with SIS 1.3, MIS-pga (delay) [12], DAG-Map [4], FlowMap [6], FlowMap -r [5, 7], Chortle-d [12] and TechMap-L =-=[38]-=-. Once again, the script used for SIS 1.3 is similar to the one proposed for MIS-pga (delay) [12]; Scr1 consists just of the technology-independent part of that script; Scr2 essentially synthesizes to... |

4 |
Cell Based Performance Optimization of Combinational Circuits
- Hinsberger, Kolla
- 1990
(Show Context)
Citation Context ...cable to a wide class of "simple" cost measures and their implementations are parameterized with the objective functions. Our approach originates from the generalization of our work about ga=-=te sizing [13, 14]-=- to technology mapping and from the observation that certain DAG-covering problems, especially duplication-free mapping, can be solved efficiently [15, 18]. This observations harmonize well with the r... |

4 |
A Cell-based Approach to Performance Optimization of Fanout-Free Circuits
- Hinsberger, Kolla
- 1992
(Show Context)
Citation Context ...cable to a wide class of "simple" cost measures and their implementations are parameterized with the objective functions. Our approach originates from the generalization of our work about ga=-=te sizing [13, 14]-=- to technology mapping and from the observation that certain DAG-covering problems, especially duplication-free mapping, can be solved efficiently [15, 18]. This observations harmonize well with the r... |

3 |
MIS: Multiplelevel interactive logic minimization
- Brayton, Rudell, et al.
- 1987
(Show Context)
Citation Context ...fferent layers and fulfilling specific process constraints. This paper describes a software platform embracing several novel approaches to technology mapping, which is the back end of logic synthesis =-=[2]-=-. The input of technology mapping is a boolean network, i.e. a directed acyclic graph, whose nodes represent elementary boolean operators (AND, OR, NOT) and whose edges represent connections. This net... |

2 |
Bestimmung geeigneter Teilnetzwerke zur Realisierung kombinatorischer Logik in FPGAs
- Salazar
- 1993
(Show Context)
Citation Context ...ferent methods for computing the sectors: Method A computes all sectors by means of a naive algorithm whereas method E just computes a sufficient subset of the sectors, the dominant sectors (see also =-=[36]-=-) by means of a flow-based algorithm. However, this more subtle method generally is not profitable. Thus, flow-based methods should be only used for computing primary sectors. Table 3 demonstrates tha... |

1 | Multi-Level Logic Synthesis Using Communication Complexity
- Hwang, Owens, et al.
- 1989
(Show Context)
Citation Context ... general target technologies was almost forgotten. However, it has been shown that decomposition techniques similar to Roth-Karp decomposition also work well for other technologies: the system factor =-=[19, 20]-=- also partitions the variables into two disjoint sets X and Y and then decomposes the function f into three (multi-output) functions ~ f , f l and f r such that f(X; Y ) = ~ f (f l (X); f r (Y )). Usi... |

1 |
Berechnung lokaler Don't Cares in booleschen Netzwerken. Master 's thesis, Universit"at W"urzburg
- Kunjan
- 1997
(Show Context)
Citation Context ...lists the results if only controllability don't cares (CDC) are used, the second block contains the results for using a set of compatible don't cares modeling controllability as well as observability =-=[25]-=-. In both cases only area-driven duplication has been done, because it is difficult to find the reason for small differences in delay (is it the use of don't cares or is it the inaccuracy of the delay... |