Simultaneous Buffer Insertion And Non-Hanan Optimization For VLSI Interconnect Under A Higher Order Awe Model (1999)
| Citations: | 4 - 2 self |
BibTeX
@MISC{Hu99simultaneousbuffer,
author = {Jiang Hu and Sachin S. Sapatnekar},
title = {Simultaneous Buffer Insertion And Non-Hanan Optimization For VLSI Interconnect Under A Higher Order Awe Model},
year = {1999}
}
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Abstract
We present a simultaneous Buffer Insertion and Non-Hanan Optimization (BINO) algorithm to improve the performance of VLSI interconnect. This algorithm aims to address the realistic situation where both the interconnect resources and timing constraints are stringent and the wire topology is to be optimized using available spaces for buffer insertions after cell placement. These spaces are fixed relative to the changing routing tree during non-Hanan optimization. The objective here is to minimize weighted sum of wire and buffer cost subject to timing constraints. In BINO, buffer insertion and non-Hanan optimization are conducted simultaneously and iteratively in a greedy fashion till the improvements are exhausted. To assure the accuracy of timing evaluation, the fourth order AWE model is employed. Experimental results on both ,18µm IC and MCM technology showed significant cost reductions.
