## FPGA Power Reduction Using Configurable Dual-Vdd (2004)

Citations: | 34 - 15 self |

### BibTeX

@MISC{Li04fpgapower,

author = {Fei Li and Yan Lin and Lei He},

title = {FPGA Power Reduction Using Configurable Dual-Vdd},

year = {2004}

}

### Years of Citing Articles

### OpenURL

### Abstract

Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a satisfactory performance and power tradeo#. We design FPGA circuits and logic fabrics using configurable dualVdd and develop the corresponding CAD flow to leverage such circuits and logic fabrics. We then carry out a highly quantitative study using area, delay and power models obtained from detailed circuit design and SPICE simulation in 100nm technology. Compared to single-Vdd FPGAs with optimized Vdd level for the same target clock frequency, configurable dual-Vdd FPGAs with full and partial supply programmability for logic blocks reduce logic power by 35.46% and 28.62% respectively and reduce total FPGA power by 14.29% and 9.04% respectively. To the best of our knowledge, it is the first in-depth study on FPGAs with configurable dual-Vdd for power reduction.

### Citations

404 |
Architecture and CAD for Deepsub-micron FPGAs
- Betz
(Show Context)
Citation Context ...er is able to customize Vdd layout for different applications, but such flexibility does not exist for the existing FPGA circuits and architectures. Assuming a generic cluster-based FPGA architecture =-=[7]-=-, we obtain the power and performance curves for MCNC benchmark circuit s38584 using Vdd scaling and dual-Vdd in Figure 1. We decide a uniform Vdd level for all clusters in Vdd scaling and use a pre-d... |

298 | FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs - Cong, Ding - 1994 |

70 | Architecture evaluation for power-efficient fpgas
- Li, Chen, et al.
- 2003
(Show Context)
Citation Context .... Copyright 2004 ACM 1-58113-828-8/04/0006 ...$5.00. Figure 1: Comparison of three power reduction solutions for benchmark s38584. and reduction of FPGA power has drawn increasing attention recently. =-=[1]-=- presented FPGA power analysis and evaluation. [2] introduced a hierarchical interconnect architecture with low-swing long wires. [3] investigated the possibility of power reduction via pre-defined du... |

47 | Low-energy embedded FPGA structures
- Kusse, Rabaey
- 1998
(Show Context)
Citation Context ...0. Figure 1: Comparison of three power reduction solutions for benchmark s38584. and reduction of FPGA power has drawn increasing attention recently. [1] presented FPGA power analysis and evaluation. =-=[2]-=- introduced a hierarchical interconnect architecture with low-swing long wires. [3] investigated the possibility of power reduction via pre-defined dual-Vdd/dual-Vt fabrics. [4] studied power-aware CA... |

42 | MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
- Kao, Narendra, et al.
- 1998
(Show Context)
Citation Context ...ed power switch 1.3v 3.46E-07 2.17E-09 1.0v 3.37E-07 9.28E-10 Table 1: Power-off state leakage for a P-block containing one 4-LUT. The power switch is similar to the sleep transistor for power gating =-=[5]-=-. An important design aspect is how to determine the trade-off between sleep transistor size and circuit delay. In our design, we control the area overhead due to power switches in three ways. First, ... |

35 |
Distributed Sleep Transistor Network for Power Reduction
- Long, He
- 2003
(Show Context)
Citation Context ... Power supply network to support configurable Vdd or dual-Vdd may introduce extra routing congestion. Leveraging our recent research on optimal synthesis of sleep transistors and power supply network =-=[12, 13]-=-, we will study power delivery design and optimization for configurable dual-Vdd FPGAs. Currently, we only apply configurable Vdd to logic blocks. The total power reduction percentage for dual-Vdd FPG... |

34 | Low-power FPGA using predefined dual-Vdd/dual-Vt fabrics
- Li, Lin, et al.
- 2004
(Show Context)
Citation Context ...d reduction of FPGA power has drawn increasing attention recently. [1] presented FPGA power analysis and evaluation. [2] introduced a hierarchical interconnect architecture with low-swing long wires. =-=[3]-=- investigated the possibility of power reduction via pre-defined dual-Vdd/dual-Vt fabrics. [4] studied power-aware CAD algorithms for conventional FPGA circuits and architectures. We believe that holi... |

23 | Pushing ASIC performance in a power envelope - Puri, Stok, et al. |

23 | Methods for true power minimization
- Brodersen, Horowitz, et al.
- 2002
(Show Context)
Citation Context ...annotating supply voltage for each logic block. We do not consider layout pattern constraint for dual-Vdd assignment and apply a sensitivity-based algorithm similar to the Vdd assignment algorithm in =-=[10]-=-. Power sensitivity with respect to supply voltage, i.e., ∆P/∆Vdd is calculated for logic blocks. The total FPGA power P includes both switching power Psw and leakage power Plkg. For each node i, we h... |

6 |
On the interaction between power-aware FPGA
- Lamoureux, Wilton
- 2003
(Show Context)
Citation Context ...alysis and evaluation. [2] introduced a hierarchical interconnect architecture with low-swing long wires. [3] investigated the possibility of power reduction via pre-defined dual-Vdd/dual-Vt fabrics. =-=[4]-=- studied power-aware CAD algorithms for conventional FPGA circuits and architectures. We believe that holistic research and development involving circuits, architectures and CAD algorithms is able to ... |

6 |
Managing Power and Performance for SOC Designs using Voltage
- Lackey
- 2002
(Show Context)
Citation Context ...to logic on critical paths and low supply voltage (VddL) to logic not on critical paths. For given performance constraints, dual-Vdd is able to achieve more power reduction than Vdd scaling for ASICs =-=[6]-=-. The ASIC designer is able to customize Vdd layout for different applications, but such flexibility does not exist for the existing FPGA circuits and architectures. Assuming a generic cluster-based F... |

2 |
Reducing Leakage Energy
- Gayasen, Tsai, et al.
- 2004
(Show Context)
Citation Context ...n experiments. and routing, we have a high average logic utilization of 84% in our experiments. But in reality, the saving by powergating can be much larger due to the much lower utilization in FPGAs =-=[11]-=-. Our arch-DV only tackles power reduction for logic blocks because it uses uniform VddH for routing resources. As shown in Table 5, the average total FPGA power savings for arch-DV with 100% P-blocks... |