FPGA Power Reduction Using Configurable Dual-Vdd (2004)
| Citations: | 28 - 12 self |
BibTeX
@MISC{Li04fpgapower,
author = {Fei Li and Yan Lin and Lei He},
title = {FPGA Power Reduction Using Configurable Dual-Vdd},
year = {2004}
}
Years of Citing Articles
Bookmark
 |
 |
 |
 |
 |
 |
OpenURL
Abstract
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a satisfactory performance and power tradeo#. We design FPGA circuits and logic fabrics using configurable dualVdd and develop the corresponding CAD flow to leverage such circuits and logic fabrics. We then carry out a highly quantitative study using area, delay and power models obtained from detailed circuit design and SPICE simulation in 100nm technology. Compared to single-Vdd FPGAs with optimized Vdd level for the same target clock frequency, configurable dual-Vdd FPGAs with full and partial supply programmability for logic blocks reduce logic power by 35.46% and 28.62% respectively and reduce total FPGA power by 14.29% and 9.04% respectively. To the best of our knowledge, it is the first in-depth study on FPGAs with configurable dual-Vdd for power reduction.
Citations
| 290 | Architecture and CAD for DeepSubmicron FPGAs - Betz, Rose, et al. - 1990 |
| 253 | Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs - Cong, Ding - 1994 |
| 49 | Architecture evaluation for powerefficient FPGAs - Li, Chen, et al. |
| 39 | Low-energy embedded FPGA structures - Kusse, Rabaey - 1998 |
| 31 | Low-power FPGA using Pre-Defined Dual-Vdd/Dual-Vt Fabrics - Li, Lin, et al. - 2004 |
| 25 | MTCMOS hierarchical sizing based on mutual exclusive discharge patterns - Kao, Narenda, et al. - 1998 |
| 20 | Distributed sleep transistor network for power reduction - Long, He - 2003 |
| 18 | Methods for True Power Minimization - Brodersen, Horowitz, et al. - 2002 |
| 17 | Pushing ASIC performance in a power envelope - Puri, Stok, et al. |
| 6 | On the interaction between power-aware FPGA - Lamoureux, Wilton - 2003 |
| 5 | Managing Power and Performance for SOC Designs using voltage islands, ICCAD - Lackey - 2002 |
| 2 | Reducing Leakage Energy - Gayasen, Tsai, et al. - 2004 |
