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An efficient VLIW DSP architecture for baseband processing (2003)
| Venue: | Proceedings of the 21st International Conference on Computer Design, IEEE Computer Society Press: Los Alamitos, CA |
| Citations: | 1 - 1 self |
BibTeX
@INPROCEEDINGS{Lin03anefficient,
author = {Tay-jyi Lin and Chin-chi Chang and Chen-chia Lee and Chein-wei Jen},
title = {An efficient VLIW DSP architecture for baseband processing},
booktitle = {Proceedings of the 21st International Conference on Computer Design, IEEE Computer Society Press: Los Alamitos, CA},
year = {2003}
}
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Abstract
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for high-performance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU) for a higher instruction issuing rate – the dramatically growing complexity in the register file (RF), and the poor code density. In this paper, we propose a novel ring-structure RF, which partitions the centralized RF into 2N sub-blocks with an explicit N-by-N switch network for N FU. Each sub-block only requires access ports for a single FU. We also propose the hierarchical VLIW encoding with variable-length RISC-like instructions and NOP removal. The ring-structure RF saves 91.88 % silicon area and reduces 77.35 % access time of the centralized RF. Our simulation results show that the proposed instruction set architecture with the exposed ring-structure RF has comparable performance with the state-of-the-art DSP processors. Moreover, the hierarchical VLIW encoding can save 32%~50 % code sizes. 1.
Keyphrases
efficient vliw dsp architecture baseband processing ring-structure rf vliw processor centralized rf access port silicon area nop removal state-of-the-art dsp processor deterministic execution time code size static instruction scheduling hierarchical vliw encoding explicit n-by-n switch network high-performance real-time dsp application register file variable-length risc-like instruction hierarchical vliw novel ring-structure rf comparable performance access time simulation result single fu functional unit major weakness poor code density
