Methodology For Early-Stage, Microarchitecture-Level Power-Performance Analysis Of Microprocessors

Methodology For Early-Stage, Microarchitecture-Level Power-Performance Analysis Of Microprocessors

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by D. Brooks , P. Bose , V. Srinivasan , M. K. Gschwind , P. G. Emma , M. G. Rosenfield

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31 - 16 self

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@MISC{Brooks_methodologyfor,
    author = {D. Brooks and P. Bose and V. Srinivasan and M. K. Gschwind and P. G. Emma and M. G. Rosenfield},
    title = {Methodology For Early-Stage, Microarchitecture-Level Power-Performance Analysis Of Microprocessors},
    year = {}
}

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Abstract

The PowerTimer toolset has been developed for use in early-stage, microarchitecture-level power-performance analysis of microprocessors.

Citations

1461	The SimpleScalar Tool Set, Version 2.0 - Burger, Austin - 1997
241	Design challenges of technology scaling - Borkar - 1999
190	Energy dissipation in general purpose microprocessors - Gonzalez, Horowitz - 1996
122	Increasing Processor Performance by Implementing Deeper Pipelines - Sprangle - 2002
110	Poweraware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors - Brooks, Schuster, et al. - 2000
110	Managing the impact of increasing microprocessor power consumption - Gunther - 2001
70	218, Yorktown Heights, New York 10598 (mkg@us.ibm.com). Dr. Gschwind is a research staff member at the Watson Research Center. He was one of the originators of the Cell Broadband Enginee architecture and the architect of the SIMD-based SPU architecture. D - Division, Center, et al.
67	The Optimum Pipeline Depth for a Microprocessor - Hartstein - 2002
59	Environment for PowerPC Microarchitecture Exploration - Moudgill, Wellman, et al. - 1999
47	Calibration of Microprocessor Performance Models - Black, Shen - 1998
27	Validation of Turandot, a Fast Processor Model for Microarchitecture Exploration - Moudgill, Bose, et al. - 1999
22	Energy optimization of multilevel cache architectures for risc and cisc processors - Ko, Balsara, et al. - 1998
16	Power-Performance Modeling and Tradeoff Analysis for a High-End Microprocessor - Brooks, Wellman, et al. - 2000
14	Wattch: A Framework for Architectural Level Power Analysis and Optimizations - Brooks, Tiwari, et al. - 2000
13	TEM 2 P 2 EST: A thermal enabled multi-model power/performance estimator - Dhodapkar, Lim, et al. - 2000
10	CPAM: A Common Power Analysis Methodology for High-Rerformance VLSI Design - Neely, Chen, et al. - 2000
6	A technique to determine power-efficient, high-performance superscalar processors - Conte, Menezes, et al. - 1995
3	Optimizing Pipelines for Power and Performance - Zyuban, Emma - 2002
2	Design and Modeling of Power-Efficient Computer Architectures - Brooks - 2001
1	Unified Methodology for Resolving Power–Performance Tradeoffs of the Microarchitectural and Circuit - RES, VOL - 2002
1	The Optimal Logic Depth per - Hrishikesh, Burger, et al. - 2002
1	Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator - Leibowitz, Schwartzburd - 1991
1	Functional Verification of a Multiple Issue - Kantrowitz, Noack - 1995
1	Testing for Function and Performance: Towards an Integrated Processor Validation Methodology - Center, Heights, et al.
1	Testing: Theory - Electron - 2000
1	Division of Engineering and Applied - Brooks - 1997
1	218, Yorktown Heights, New York 10598 (viji@us.ibm.com). Dr. Srinivasan joined the IBM Thomas J. Watson Research Center in 2001 as a Research Staff Member. She received a B.S. degree in physics from the University of Madras in 1990, an M.S. degree in comp - Division, Center, et al.
1	he has contributed to several generations of binary translation architectures exploiting instruction-level parallelism, the evaluation of future microarchitecture options for current architectures. He was one of the originators of the supercomputer-on-a-c - IBM - 1996
1	is currently Director of the Austin Research Laboratory, focusing on highperformance VLSI design and tools, system-level power analysis, and new system architectures. He was previously Senior Manager of VLSI Design and Architecture at the IBM Thomas J. Wa - Rosenfield - 1993