Abstract

In property-based formal verification, a natural question that often arises is 'Have we specified enough properties?' In this paper, we provide a way of approximating an answer to this question. We present a relatively cheap analysis that, given the interface of a design under verification, plus a formal safety property list, identifies cases where some outputs of the design are not constrained at all by the properties. For practical reasons, we also provide an easy way for the verification engineer to explicitly state that certain outputs are allowed to be underconstrained.

Citations