RTL Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic Model Checking

RTL Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic Model Checking (1997)

by Vida Vakilotojar , Peter A. Beerel

Venue:	Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'97
Citations:	4 - 1 self

BibTeX

@INPROCEEDINGS{Vakilotojar97rtlverification,
    author = {Vida Vakilotojar and Peter A. Beerel},
    title = {RTL Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic Model Checking},
    booktitle = {Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'97},
    year = {1997}
}

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Abstract

This paper describes a tool-supported methodology for the register-transfer-level formal verification of a growing hardware design paradigm--timed asynchronous systems. These systems are a network of communicating asynchronous and synchronous components and have correctness constraints that depend on specified bounded delays. This paper formalizes the verification problem and demonstrates how time-discretization, abstraction, and non-determinism can lead to a system model comprised of communicating finite state machines composed synchronously. The paper then describes a translator that accepts structural VHDL system description along with controller specifications and generates the input to a symbolic model checker (SMV). Finally, we describe two case studies in which concurrent verification and design led to the correction of many errors not easily found using simulation. I. INTRODUCTION Asynchronous design techniques have long promised systems which have low-power, low average-case ...

Citations

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