## RTL Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic Model Checking (1997)

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Venue: | Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'97 |

Citations: | 4 - 1 self |

### BibTeX

@INPROCEEDINGS{Vakilotojar97rtlverification,

author = {Vida Vakilotojar and Peter A. Beerel},

title = {RTL Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic Model Checking},

booktitle = {Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'97},

year = {1997}

}

### Years of Citing Articles

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### Abstract

This paper describes a tool-supported methodology for the register-transfer-level formal verification of a growing hardware design paradigm--timed asynchronous systems. These systems are a network of communicating asynchronous and synchronous components and have correctness constraints that depend on specified bounded delays. This paper formalizes the verification problem and demonstrates how time-discretization, abstraction, and non-determinism can lead to a system model comprised of communicating finite state machines composed synchronously. The paper then describes a translator that accepts structural VHDL system description along with controller specifications and generates the input to a symbolic model checker (SMV). Finally, we describe two case studies in which concurrent verification and design led to the correction of many errors not easily found using simulation. I. INTRODUCTION Asynchronous design techniques have long promised systems which have low-power, low average-case ...

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Citation Context ...afety, liveness, and fairness to be specified in a concise syntax. SMV uses OBDD-based symbolic model-checking algorithm to efficiently determine whether specifications expressed in CTL are satisfied =-=[9]-=-. In SMV, system components are specified as modules connected to and interacting with each other. The behavior of each module, in terms of its response to its input stimuli, and its timing characteri... |

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Citation Context ...makes ensuring correctness via simulation more difficult, motivating the need for formal verification. While numerous tools and techniques have been developed for verifying speed-independent circuits =-=[3, 4, 5, 6, 7, 8]-=-, verifying asynchronous circuits with timing assumptions has been rather limited. Burch [9, 10, 11] and Rokicki et al. [12] have verified gatelevel timed circuits and Yoneda et al. [13] have verified... |

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Citation Context ...makes ensuring correctness via simulation more difficult, motivating the need for formal verification. While numerous tools and techniques have been developed for verifying speed-independent circuits =-=[3, 4, 5, 6, 7, 8]-=-, verifying asynchronous circuits with timing assumptions has been rather limited. Burch [9, 10, 11] and Rokicki et al. [12] have verified gatelevel timed circuits and Yoneda et al. [13] have verified... |

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Citation Context ...makes ensuring correctness via simulation more difficult, motivating the need for formal verification. While numerous tools and techniques have been developed for verifying speed-independent circuits =-=[3, 4, 5, 6, 7, 8]-=-, verifying asynchronous circuits with timing assumptions has been rather limited. Burch [9, 10, 11] and Rokicki et al. [12] have verified gatelevel timed circuits and Yoneda et al. [13] have verified... |

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Citation Context ...[3, 4, 5, 6, 7, 8], verifying asynchronous circuits with timing assumptions has been rather limited. Burch [9, 10, 11] and Rokicki et al. [12] have verified gatelevel timed circuits and Yoneda et al. =-=[13]-=- have verified time Petri nets, but all their approaches have been limited to small examples due to the state explosion problem associated with their underlying explicit state techniques. To handle la... |

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Citation Context ...ynchronous and heterogeneous systems, including data path components with data-dependent delays (i.e., adders/multipliers), distributed asynchronous control circuits (i.e., XBM burst-mode controllers =-=[17]-=-), and interface gluelogic (i.e., mutual-exclusion elements). The paper then describes the verification problems specific to RTL design we have addressed. We focus on the timed hardware protocol verif... |

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Citation Context ...differential equation solver design that is almost 50% faster on average than any comparable synchronous design [1], and efficient pausible clocking strategies for interfacing different clock domains =-=[2]-=-. These recent successes among others are finally demonstrating the potential advantages of using asynchronous design techniques. However, the increased usage of timing assumptions, both local and glo... |

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Citation Context ...e numerous tools and techniques have been developed for verifying speed-independent circuits [3, 4, 5, 6, 7, 8], verifying asynchronous circuits with timing assumptions has been rather limited. Burch =-=[9, 10, 11]-=- and Rokicki et al. [12] have verified gatelevel timed circuits and Yoneda et al. [13] have verified time Petri nets, but all their approaches have been limited to small examples due to the state expl... |

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Citation Context ...raints of the environment component. Currently, we have focused on timed systems that use XBM burst-mode machines as the sole type of controllers, however extensions to other controller design styles =-=[11, 10]-=- are straightFSM 1 FSM 2 ME 1 ME 2 FF1 FF2 Req1 Ack1 Req2 Ack2 Clk Req1s Ack1s Req2s Ack2s Synchronous System Asynch System1 Asynch System2 Interface Circuitry Fig. 1. A pausible clocking interface, a... |

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Citation Context ...on. While numerous tools and techniques have been developed for verifying speed-independent circuits [3, 5, 8, 2, 12], verifying asynchronous circuits with timing assumptions has been rather limited. =-=[4, 10, 13]-=- have addressed verifying gate-level timed circuits, but their techniques have been limited to small circuits due to the state explosion problem associated with their underlying explicit state techniq... |

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Citation Context ... have been developed for verifying speed-independent circuits [3, 4, 5, 6, 7, 8], verifying asynchronous circuits with timing assumptions has been rather limited. Burch [9, 10, 11] and Rokicki et al. =-=[12]-=- have verified gatelevel timed circuits and Yoneda et al. [13] have verified time Petri nets, but all their approaches have been limited to small examples due to the state explosion problem associated... |

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Citation Context ...e numerous tools and techniques have been developed for verifying speed-independent circuits [3, 4, 5, 6, 7, 8], verifying asynchronous circuits with timing assumptions has been rather limited. Burch =-=[9, 10, 11]-=- and Rokicki et al. [12] have verified gatelevel timed circuits and Yoneda et al. [13] have verified time Petri nets, but all their approaches have been limited to small examples due to the state expl... |

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2 |
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Citation Context ...h decoder that is approximately three times faster than the current state of the art, a differential equation solver design that is almost 50% faster on average than any comparable synchronous design =-=[1]-=-, and efficient pausible clocking strategies for interfacing different clock domains [2]. These recent successes among others are finally demonstrating the potential advantages of using asynchronous d... |

2 |
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Citation Context ...ir approaches have been limited to small examples due to the state explosion problem associated with their underlying explicit state techniques. To handle larger gate-level circuits, Hamaguchi et al. =-=[14]-=- advocate implicit state techniques and we apply some of their modeling techniques to the register-transfer level (RTL). Hamaguchi et al. [14] focuses on verifying hazard-freedom. This paper, however,... |

1 |
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Citation Context ...e numerous tools and techniques have been developed for verifying speed-independent circuits [3, 4, 5, 6, 7, 8], verifying asynchronous circuits with timing assumptions has been rather limited. Burch =-=[9, 10, 11]-=- and Rokicki et al. [12] have verified gatelevel timed circuits and Yoneda et al. [13] have verified time Petri nets, but all their approaches have been limited to small examples due to the state expl... |