The APIC Approach to High Performance Network Interface Design: Protected DMA and Other Techniques (1997) [54 citations — 2 self]
http://king.ccrc.wustl.edu/~zubin/infocom97-LONG.p
http://www.arl.wustl.edu/arl/Publications/ps/zubin
http://www.arl.wustl.edu/arl/TechRpts/1996/wucs-96
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author = {Zubin D. Dittia and Guru M. Parulkar and Jerome R. Cox and Jr.},
title = {The APIC Approach to High Performance Network Interface Design: Protected DMA and Other Techniques},
booktitle = {IN PROCEEDINGS OF INFOCOM '97},
year = {1997},
pages = {179--187},
publisher = {}
}
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Abstract:
We are building a very high performance 1.2 Gb/s ATM network interface chip called the APIC (ATM Port Interconnect Controller). In addition to borrowing useful ideas from a number of research and commercial prototypes, the APIC design embraces several innovative features, and integrates all of these pieces into a coherent whole. This paper describes some of the novel ideas that have been incorporated in the APIC design with a view to improving the bandwidth and latency seen by end-applications. Among the techniques described, Protected DMA and Protected I/O were designed to allow applications to queue data for transmission or reception directly from user-space, effectively bypassing the kernel. This argues for moving the entire protocol stack including the interface device driver into user-space, thereby yielding better latency and throughput performance than kernel-resident implementations. Pool DMA when used with Packet Splitting, is a technique that can be used to build true zero-...
