Abstract

During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. In this paper we concentrate on techniques to model the feasibility region. The methodology is general and can be used for both analog and digital circuits. Macromodels are developed and verified for analog blocks at different levels of hierarchy. 1 Hierarchical Circuit Design An increasing percentage of IC's have analog circuit designs in them. These and other requirements stress the need for automatic synthesis tools for analog circuits. Hierarchy plays a significant role in the design of digital and analog circuits. A large design can be broken up into smaller sub-blocks at the different levels of a hierarchy. An example hierarchy for an A/D converter ...

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