Retiming Sequential Circuits for Low Power (1993)
| Venue: | In Proceedings of the Int'l Conference on Computer-Aided Design |
| Citations: | 63 - 7 self |
BibTeX
@INPROCEEDINGS{Monteiro93retimingsequential,
author = {José Monteiro and Srinivas Devadas and Abhijit Ghosh},
title = {Retiming Sequential Circuits for Low Power},
booktitle = {In Proceedings of the Int'l Conference on Computer-Aided Design},
year = {1993},
pages = {398--402}
}
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Abstract
Switching activity is the primary cause of power dissipation in CMOS combinational and sequential circuits. We give a method of estimating power in pipelined sequential CMOS circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous sequential circuit can be significantly less than the activity at the flip-flop inputs. We present a retiming method that targets the power dissipation of a sequential circuit. 1 Introduction For many consumer electronic applications low average power dissipation is desirable and for certain special applications low power dissipation is of critical importance. For applications such as personal communication systems like hand-held mobile telephones, lowpower dissipation may be the tightest constraint in the design. More generally, with the increasing scale of integration, we believe tha...
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