## Abstraction Mechanisms for Hardware Verification (1987)

Venue: | VLSI Specification, Verification and Synthesis |

Citations: | 39 - 0 self |

### BibTeX

@INPROCEEDINGS{Melham87abstractionmechanisms,

author = {Thomas Melham},

title = {Abstraction Mechanisms for Hardware Verification},

booktitle = {VLSI Specification, Verification and Synthesis},

year = {1987},

pages = {129--157},

publisher = {Kluwer Academic Publishers}

}

### OpenURL

### Abstract

ion Mechanisms for Hardware Verification Thomas F. Melham University of Cambridge Computer Laboratory New Museums Site, Pembroke Street Cambridge, CB2 3QG, England Abstract: It is argued that techniques for proving the correctness of hardware designs must use abstraction mechanisms for relating formal descriptions at different levels of detail. Four such abstraction mechanisms and their formalization in higher order logic are discussed. Introduction Recent advances in microelectronics have given designers of digital hardware the potential to build electronic devices of unprecedented size and complexity. With increasing size and complexity, however, it becomes increasingly difficult to ensure that such systems will not malfunction because of design errors. This problem has prompted some researchers to look for a firm theoretical basis for correct design of hardware systems. Mathematical methods have been developed to model the functional behaviour of electronic devices and to verify,...

### Citations

64 | HOL a machine oriented formulation of higher order logic
- Gordon
- 1985
(Show Context)
Citation Context ...dapted for this purpose by Mike Gordon at the University of Cambridge. In this section, a very brief introduction is given to this logic; a more complete and formal presentation is given by Gordon in =-=[2, 3]-=-. An overview is then given of the basic techniques for specifying the behaviour and structure of digital hardware using higher order logic. 3.1 Introduction to Higher Order Logic Higher order logic i... |

27 |
HOL: A Proof Generating System for Higher Order Logic
- Gordon
- 1989
(Show Context)
Citation Context ...dapted for this purpose by Mike Gordon at the University of Cambridge. In this section, a very brief introduction is given to this logic; a more complete and formal presentation is given by Gordon in =-=[2, 3]-=-. An overview is then given of the basic techniques for specifying the behaviour and structure of digital hardware using higher order logic. 3.1 Introduction to Higher Order Logic Higher order logic i... |

23 |
Specification and verification using higher-order logic: A case study
- Hanna, Daeche
- 1986
(Show Context)
Citation Context ... when p; q when p) 3 For clarity, a greatly simplified specification of Dtype is used in this example. For D-type flip flop specifications that include information about detailed timing behaviour see =-=[6]-=- or [8]. 22 Abstraction Mechanisms for Hardware Verification The trouble is that the abstract time scale for Del must be defined in terms of the value of the clock ck. Informally, Dtype implements a u... |

15 |
Hardware Verification using Higher Order Logic
- Camilleri, Gordon, et al.
- 1987
(Show Context)
Citation Context ...the existential quantifier and proving that the resulting term is logically equivalent to the specification. This technique of using `9' to hide internal structure is fairly common; see, for example, =-=[1, 4]-=- or [9]. 4.1 An Example This example illustrates the use of structural abstraction in a very simple correctness proof. A delay device with ffi time units of delay can be specified by the predicate Del... |

13 |
Specification and verification of digital systems using higher-order predicate logic
- Hanna, Daeche
- 1986
(Show Context)
Citation Context ....2 Specifying Behaviour in Logic The technique for specifying hardware behaviour with higher order logic is well established; see, for example, Gordon's paper [4] or the work done by Hanna and Daeche =-=[7]-=-. Hardware devices can be specified by predicates that describe their behaviour in terms of the values on their external ports. Consider, for instance, a device with external ports a, b, c and d: Dev ... |

8 |
Describing and designing circuits by means of a synchronous declarative language
- Halbwachs, Lonchampt, et al.
- 1986
(Show Context)
Citation Context ...tness given above must be modified in practice. 2 In previous work, I have called this operator `Abs'. The mnemonicly superior name `when' was suggested by the work of Halbwachs, Lonchampt and Pilaud =-=[5]-=-. Abstraction Mechanisms for Hardware Verification 21 7.2 An Example A commonly used register-transfer level device is the unit delay: Del in out which can by specified in higher order logic by: Del(i... |

6 |
Why higher order logic is a good formalism for specifying and verifying hardware
- Gordon
- 1986
(Show Context)
Citation Context ...ion of the "-operator, see [2] or [10]. 3.2 Specifying Behaviour in Logic The technique for specifying hardware behaviour with higher order logic is well established; see, for example, Gordon's p=-=aper [4]-=- or the work done by Hanna and Daeche [7]. Hardware devices can be specified by predicates that describe their behaviour in terms of the values on their external ports. Consider, for instance, a devic... |

4 |
Models and logic of MOS circuitsâ€™, in: Logic of Programming and Calculi of Discrete Design: International Summer School Directed by
- Winskel
- 1987
(Show Context)
Citation Context ... can be described by the 1 This model of transistor behaviour is, of course, very much simplified---but it will serve for the purposes of this example. For a better transistor model see, for example, =-=[11]-=- 14 Abstraction Mechanisms for Hardware Verification predicate Imp, defined as follows: Imp(i; o) j 9 p g: Pwr(p)sGnd(g)sPtran(i; p; o)sNtran(i; g; o) The predicate Imp defines the behaviour of the in... |

2 |
Application of Formal Methods to Digital System Design
- Herbert
- 1986
(Show Context)
Citation Context ...; q when p) 3 For clarity, a greatly simplified specification of Dtype is used in this example. For D-type flip flop specifications that include information about detailed timing behaviour see [6] or =-=[8]-=-. 22 Abstraction Mechanisms for Hardware Verification The trouble is that the abstract time scale for Del must be defined in terms of the value of the clock ck. Informally, Dtype implements a unit del... |

1 |
A Calculus of Total Correctness for Communicating
- Hoare
- 1981
(Show Context)
Citation Context ...ntial quantifier and proving that the resulting term is logically equivalent to the specification. This technique of using `9' to hide internal structure is fairly common; see, for example, [1, 4] or =-=[9]-=-. 4.1 An Example This example illustrates the use of structural abstraction in a very simple correctness proof. A delay device with ffi time units of delay can be specified by the predicate Delay, def... |