High-Level Synthesis Techniques for Reducing the Activity of Functional Units (1995)
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BibTeX
@MISC{Musoll95high-levelsynthesis,
author = {Enric Musoll and Enric Musoll and Jordi Cortadella and Jordi Cortadella and E. Musoll and J. Cortadella},
title = {High-Level Synthesis Techniques for Reducing the Activity of Functional Units},
year = {1995}
}
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Abstract
Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during high-level synthesis (high-level transformations, scheduling and binding). Several techniques pursuing low power are proposed and the potential benefits evaluated. The common idea behind these techniques is to reduce the activity of the functional units (e.g. adders, multipliers) by minimizing the changes of their input operands. Preliminary evaluations obtained from switch-level simulations show that significant improvements can be achieved. 1 Introduction Power consumption can be taken into account at different levels [5]: technological, topological, architectural and algorithmic level. High-level synthesis (HLS) comprises techniques at the architectural and algorithmic level. Traditionally, HLS has been applied to obtain small and fast designs. But little has been done ...
