Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets (1996)
| Venue: | In 16th Int. Conf. on Application and Theory of Petri Nets, volume 935 of LNCS |
| Citations: | 19 - 3 self |
BibTeX
@INPROCEEDINGS{Roig96verificationof,
author = {Oriol Roig and Jordi Cortadella and Enric Pastor},
title = {Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets},
booktitle = {In 16th Int. Conf. on Application and Theory of Petri Nets, volume 935 of LNCS},
year = {1996},
pages = {374--391},
publisher = {Springer-Verlag}
}
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Abstract
. This paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification and the gate-level network behavior by means of boolean functions. These functions are efficiently handled by using Binary Decision Diagrams. Algorithms for verifying the correctness of designs, as well as several circuit properties are proposed. Finally, the applicability of our verification method has been proven by checking the correctness of different benchmarks. 1 Introduction During these last few years, asynchronous circuits have gained interest due to their promising advantages, such as local synchronization, elimination of the clock skew problem, faster and less power-consuming circuits, and high degree of modularity. However, the concurrent nature of asynchronous circuits makes them difficult to design because all transitions must be taken into account ...
