Abstract

In analog system design, final verification in the presence of parasitic loading effects is crucial to guarantee functionality of the entire circuit. In this paper, we present a methodology for analog system verification in the presence of parasitics using behavioral simulation. When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster. 1 Introduction We have proposed a constraint-driven, top-down design methodology for mixed-mode systems[1] that is supported by analog design tools. An integral part of such methodology is the complete verification of the synthesized circuit in the presence of parasitics due to routing, supply variations, and coupling. Because parasitics degrade analog system performance, it is crucial to verify by simulation as completely as possible the circuit functionality in the presence of these second order effects. Existing design methodologies, manual or automatic [2, 3,...

Citations