## Design Considerations for CMOS Digital Circuits with Improved Hot-Carrier Reliability (1996)

Venue: | IEEE Journal of Solid-State Circuits |

Citations: | 12 - 0 self |

### BibTeX

@ARTICLE{Leblebici96designconsiderations,

author = {Yusuf Leblebici},

title = {Design Considerations for CMOS Digital Circuits with Improved Hot-Carrier Reliability},

journal = {IEEE Journal of Solid-State Circuits},

year = {1996},

volume = {31},

pages = {1014--1024}

}

### OpenURL

### Abstract

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F ) (F ) (F ) and the transistor aspect ratio (r)(r)(r) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. A...

### Citations

34 |
A Unified Design Methodology for CMOS Tapered Buffers
- Cherkauer, Friedman
- 1995
(Show Context)
Citation Context ...rter stages are identical. The overall propagation delay of the scaled buffer is usually optimized by calculating the scaling factor , for which the propagation delay achieves its minimum [10], [11], =-=[13]-=-. The degradation macro-model presented in Section II for the simple CMOS inverter circuit can now be applied to the scaled inverter-chain structure. To accomplish this, the two design parameters iden... |

8 |
Hot-electron-induced MOSFET degradation—Model, monitor, and improvement
- Hu, Tam, et al.
- 1985
(Show Context)
Citation Context ...tric field (hot-carriers) may be injected into the gate oxide and cause permanent changes in the oxide-interface charge distribution, hence degrading the current-voltage characteristics of the MOSFET =-=[1]-=-, [2]. Since the likelihood of hot-carrier induced degradation increases with shrinking device dimensions, this problem was identified as one of the important factors that may impose strict limitation... |

5 |
S.M.Kang, “Hot-carrier reliability of MOS VLSI circuits
- Leblebici
- 1993
(Show Context)
Citation Context ...he total output node voltage, the hot-carrier constraints on the other switching transistors in the circuit can be relaxed. Fig. 14 shows some of the circuit-level reliability measures discussed here =-=[15]-=-. VI. CONCLUSION In this paper, a parametric reliability measure has been presented for estimating the transient performance degradation in CMOS digital circuits. Delay-time degradation is shown to be... |

3 |
Reliability issues of MOS and bipolar ICs
- Hu
- 1989
(Show Context)
Citation Context ...tion increases with shrinking device dimensions, this problem was identified as one of the important factors that may impose strict limitations on maximum achievable device densities in VLSI circuits =-=[3]-=-, [4]. The concept of gradual circuit performance degradation as a result of device aging must be carefully investigated in order to assess the true impact of hot-carrier effects. One of the problems ... |

3 |
Performance and reliability design issues for deep-submicrometer MOSFET’s
- Chung, Jeng, et al.
- 1991
(Show Context)
Citation Context ...increases with shrinking device dimensions, this problem was identified as one of the important factors that may impose strict limitations on maximum achievable device densities in VLSI circuits [3], =-=[4]-=-. The concept of gradual circuit performance degradation as a result of device aging must be carefully investigated in order to assess the true impact of hot-carrier effects. One of the problems encou... |

2 |
Modeling and Simulation of Hot-Carrier Induced Device Degradation in MOS Circuits
- Leblebici, Kang
- 1992
(Show Context)
Citation Context ...nce. Most of the previous efforts to evaluate device and circuit degradation have focused on using circuit-level simulation tools such as some modified variants of SPICE and SPICElike simulators [5]--=-=[7]-=-. These reliability simulation tools can be used to assess and to evaluate long-term circuit degradation and to improve the reliability by incremental design modifications. However, there is a growing... |

1 |
The relationship between oxide charge and device degradation: A comparative study of n- and p-channel MOSFET's
- Schwerin, Haensch, et al.
- 1987
(Show Context)
Citation Context ...field (hot-carriers) may be injected into the gate oxide and cause permanent changes in the oxide-interface charge distribution, hence degrading the current-voltage characteristics of the MOSFET [1], =-=[2]-=-. Since the likelihood of hot-carrier induced degradation increases with shrinking device dimensions, this problem was identified as one of the important factors that may impose strict limitations on ... |

1 |
Circuit aging simulator (CAS
- Lee, Kuo, et al.
- 1988
(Show Context)
Citation Context ...formance. Most of the previous efforts to evaluate device and circuit degradation have focused on using circuit-level simulation tools such as some modified variants of SPICE and SPICElike simulators =-=[5]-=---[7]. These reliability simulation tools can be used to assess and to evaluate long-term circuit degradation and to improve the reliability by incremental design modifications. However, there is a gr... |

1 |
An integrated-circuit reliability simulator---RELY
- Sheu, Hsu, et al.
- 1989
(Show Context)
Citation Context ...erface traps near the drain [7], [9]. The time-dependent increase of the interface trap density can be described as a simple function of the average bond-breaking current density over one period [5], =-=[6]-=-. The bond-breaking current density is defined as , where and represent the drain current and the substrate current, respectively, and represents the channel width of the MOS transistor. Since the amo... |

1 |
Parametric macro-modeling of hot-carrier induced dynamic degradation in MOS VLSI circuits
- Leblebici, Sun, et al.
- 1993
(Show Context)
Citation Context ...es will become essential for reliable design of submicron CMOS structures. A simple parametric macro-modeling approach for the estimation of device degradation based on device geometries was given in =-=[8]-=-. In this paper, the parametric macro-model for reliability estimation is extended to include parasitic gate-drain overlap capacitances and the effects of the resulting drain voltage overshoots. Also,... |

1 |
Dynamic degradation in MOSFET's---Part II: Application in the circuit environment
- Weber, Brox, et al.
- 1991
(Show Context)
Citation Context ...e-interface charge distribution. In digital logic circuits, the degradation of the MOS current-voltage characteristics is attributed primarily to the generation of interface traps near the drain [7], =-=[9]-=-. The time-dependent increase of the interface trap density can be described as a simple function of the average bond-breaking current density over one period [5], [6]. The bond-breaking current densi... |

1 |
Hotcarrier -reliability design guidelines for CMOS logic circuits
- Quader, Minami, et al.
- 1994
(Show Context)
Citation Context ... conditions. The relationship between the device current degradation and the transient performance degradation given in (9) is a more accurate model compared to the simple linear relationship used in =-=[12]-=-, and it takes into account the different degradation rates for propagation delay and fall time. IV. DESIGN GUIDELINES FOR TAPERED (SCALED)BUFFER CIRCUITS The tapered buffer structure consisting of a ... |

1 |
Design considerations for tapered CMOS inverter chains with improved hot-carrier reliability
- Leblebici
- 1995
(Show Context)
Citation Context ...n of the CMOS inverter, namely the - ratio and the input signal slope, must be expressed in terms of the scaling factor. First, consider the-ratio of the th inverter stage. This ratio is expressed as =-=[14]-=- (10) where represents the scaling factor and represents the aspect ratio of the MOS and MOS transistors. Notice that the-ratio is identical for all stages in the buffer chain. Now consider the rising... |