Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System (1998)
| Venue: | In Power Driven Microarchitecture Workshop, attached to ISCA98 |
| Citations: | 43 - 0 self |
BibTeX
@INPROCEEDINGS{Pering98dynamicvoltage,
author = {Trevor Pering and Tom Burd and Robert Brodersen},
title = {Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System},
booktitle = {In Power Driven Microarchitecture Workshop, attached to ISCA98},
year = {1998}
}
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Abstract
This paper describes the design of a low-power microprocessor system that can run between 8Mhz at 1.1V and 100MHz at 3.3V. The ramifications of Dynamic Voltage Scaling, which allows the processor to dynamically alter its operating voltage at run-time, will be presented along with a description of the system design and an approach to benchmarking. In addition, a more in-depth discussion of the cache memory system will be given. 1. Introduction Our design goal is the implementation of a lowpower microprocessor for embedded systems. It is estimated that the processor will consume 1.8mW at 1.1V/ 8MHz and 220mW at 3.3V/100MHz using a 0.6 µm CMOS process. This paper discusses the system design, cache optimization, and the processor's Dynamic Voltage Scaling (DVS) ability. In CMOS design, the energy-per-operation is given by the equation where C is the switched capacitance and V is the operating voltage [2]. To minimize , we use aggressive low-power design techniques to reduce C and DVS to...
