High-Speed CMOS Switch Designs for Free-Space Optoelectronic MINs (1995)
| Venue: | IEEE Transactions on VLSI |
| Citations: | 4 - 3 self |
BibTeX
@ARTICLE{Kibar95high-speedcmos,
author = {Osman Kibar and Philippe J. Marchand and Osman Kibar and Osman Kibar and Osman Kibar and Sadik C. Esener and Sadik C. Esener and Sadik C. Esener},
title = {High-Speed CMOS Switch Designs for Free-Space Optoelectronic MINs},
journal = {IEEE Transactions on VLSI},
year = {1995},
volume = {6},
pages = {372--386}
}
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Abstract
We present the theory, experimental results, and analytical modeling of high-speed CMOS switches, with a 2-D layout, suitable for the implementation of packet-switched free-space optoelectronic Multistage Interconnection Networks (MINs). These switches are fully connected, bi-directional, and scaleable. The first design is a proof of concept of the half-switch, which is a two-to-one multiplexer, and the 2-D layout. The second design introduces a novel self-routing concept, with contention detection and packet drop-and-resend capabilities. It uses three-valued logic, with 2.5V being the third value for a 5V power supply. Simulations show that for a 0.8 µm CMOS technology the switches can operate at speeds up to 250 Mbits/sec. Scaled-down versions of both designs have been successfully implemented in 2.0 µm CMOS. The analytical modeling of the switches show that large scale free-space optoelectronic MINs using this concept could offer close to Terabit/sec throughput capabilities and ver...
Keyphrases
free-space optoelectronic min high-speed cmos switch design analytical modeling 2-d layout terabit sec throughput capability second design contention detection large scale free-space optoelectronic min power supply three-valued logic scaled-down version novel self-routing concept third value packet drop-and-resend capability high-speed cmos switch cmos technology first design experimental result two-to-one multiplexer
