Abstract

Many modern computer processors are based on an out-of-order superscalar execution model. These processors make use of a sophisticated dynamic issue mechanism that reorders the program instructions at execution time to overcome hazards and expose more Instruction-Level Parallelism (ILP). However, this valuable mechanism is ignored by the compilers commonly used on these architectures. For a given program, the current compiler technology focuses on exposing as much ILP as possible without taking into consideration the instruction reordering performed by the processor at runtime. This thesis presents a novel approach to the instruction scheduling problem for dynamic issue processors. Our approach aims at generating an instruction sequence with a low register pressure and a high level of ILP exploitable by the dynamic issue mechanism of the processor. Our objective is to improve the performance of the program by taking advantage of the out-of-order execution and register renaming mechanis...

Citations