## Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations and Their Resolution (1995)

### Cached

### Download Links

- [power.csl.uiuc.edu]
- [www.eecg.utoronto.ca]
- [www.eecg.toronto.edu]
- DBLP

### Other Repositories/Bibliography

Venue: | IEEE Transactions on Computer-Aided Design |

Citations: | 43 - 8 self |

### BibTeX

@ARTICLE{Kriplani95patternindependent,

author = {Harish Kriplani and Farid Najm and Ibrahim Hajj},

title = {Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations and Their Resolution},

journal = {IEEE Transactions on Computer-Aided Design},

year = {1995},

volume = {14},

pages = {998--1012}

}

### OpenURL

### Abstract

Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a patternindependent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient an...

### Citations

728 |
Heuristics: Intelligent Search Strategies for Computer Problem Solving
- Pearl
- 1984
(Show Context)
Citation Context ...ating inputs in an intelligent fashion, we can significantly improve the iMax upper bound, without spending too much cpu time. We have developed an algorithm based on best first search (BFS) approach =-=[18]-=- that is very effective in selecting and enumerating inputs and thereby improving the upper bound on maximum voltage drop. Before describing the details of the algorithm, we note that both PIE and the... |

445 |
Introduction to VLSI Systems
- Mead, Conway
- 1980
(Show Context)
Citation Context ...s) and degradation in switching speeds. Severity of the voltage drop problems intensify with the continuing push for denser chips and finer technologies. As is known from the classical scaling theory =-=[1]-=-, as the minimum feature size and supply voltage are scaled down, while the total power dissipation on the chip remains constant, the currents flowing in the P&G buses increase. With higher currents f... |

358 |
A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran
- Brglez, Fujiwara
- 1985
(Show Context)
Citation Context ...7 3.32 1.71 27.8s 12h 48m c6288 2672 32 126 8.65 6.21 1.39 46.2s 47h 32m c7552 5066 207 247 11.52 7.49 1.54 48.4s 26h 36m In Table 2, we report similar results for the ten ISCAS-85 benchmark circuits =-=[16]-=-. These circuits have number of gates ranging from 218 to 5066 and all the circuits have at least 32 inputs. In the table, in the last two columns, we document the cpu times needed by the iMax algorit... |

338 |
Combinational profiles of sequential benchmark circuits
- Brglez, Bryan, et al.
- 1989
(Show Context)
Citation Context ...oduce a good upper bound. In order to demonstrate the applicability of the PIE algorithm for large circuits with several thousand gates, we have also experimented with the ISCAS-89 benchmark circuits =-=[19]-=-. For 0.8 1 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 0 200 400 600 800 1000 R A T I O S nodes UB/LB s s ssss ssssssss ssss ssssssssssss ssss ssss ssss ssss ssss ssss ss ss ss ss ss ss ss ssss ss ss ss ss s... |

307 |
Switching and Finite Automata Theory
- Kohavi
- 1970
(Show Context)
Citation Context ...OT, it is easy to verify that the output of the gate is as shown in Fig. 5. In fact, the set (l, h, hl, lh) along with the above definitions for AND, OR and NOT constitutes a 4-values Boolean algebra =-=[13]-=-. The output of a gate realizing any arbitrary Boolean function can be easily calculated by repeated applications of the above. By calculating the output of the gate for each and every input pattern, ... |

93 |
Computer-Aided Analysis of Electronic Circuits
- Chua, Lin
- 1975
(Show Context)
Citation Context ... vector of voltage drops appearing at its nodes (V ) is related to the corresponding vector of contact point currents (I) as follows : Y V = I (2) where Y is the node admittance matrix of the network =-=[15]-=-. When the bus is represented by an RC network, the following relationship holds Y V = I \Gamma C V (3) where C is the diagonal matrix of node capacitances. By calculating the LU factors of the Y matr... |

75 |
Basic Circuit Theory
- Desoer, Kuh
- 1969
(Show Context)
Citation Context ... n X j=1 j 6=i y ij v j (t) 3 7 5 (17) Now, c i ? 0, I i (t)s0, v j (t)s0 for j = 1; 2; : : : n; j 6= i and y ij ; i 6= j being the off-diagonal terms of the node admittance matrix Y are all negative =-=[22]-=-. Hencesv i (t)s0. In the following theorem, for vectors X and Y , we use the notation XsY to mean that vector X is element-wise less than or equal to Y , i.e., x isy i ; 1sisn. Theorem 1 If the vecto... |

55 | Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation
- DEVADAS, KEUTZER, et al.
- 1992
(Show Context)
Citation Context ... bound search technique is slow on large circuits. Furthermore, their heuristic approach does not guarantee an upper bound on the maximum currents. Devadas et. al. have addressed a similar problem in =-=[9]-=-. They consider the estimation of worst case power dissipation in CMOS combinational circuits. They reduce this problem to a weighted max-satisfiability problem on a set of multi-output Boolean functi... |

37 |
K.: Combinational Pro_les of Sequential Bench-mark Circuits
- Brglez, Bryan, et al.
- 1989
(Show Context)
Citation Context ...oduce a good upper bound. In order to demonstrate the applicability of the PIE algorithm for large circuits with several thousand gates, we have also experimented with the ISCAS-89 benchmark circuits =-=[19]-=-. For 29sR A T I O 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1 s 0.8 0 200 400 600 800 1000 S nodes UB/LB s s s s s s sssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss ssss Figure 14: U pp... |

31 | Crest - a current estimator for cmos circuits
- Najm, Burch, et al.
- 1988
(Show Context)
Citation Context ...ither directly fed by n or is connected to the output of a gate that is in FOC. One technique to partially enumerate the internal nodes of a circuit, called Multi-Cone Analysis (MCA), was reported in =-=[17]-=-. The motivation behind such an approach was to be able to enumerate at the MFO nodes, which are the sources of the signal correlation problem. The approach involves partitioning the circuit in a fash... |

26 |
Time Domain Current Waveform Simulation
- Deng, Shiau, et al.
(Show Context)
Citation Context ... along with extensive experimental results on several benchmark circuits. Finally, in section 9, conclusions and some guidelines for future work are presented. 2 Previous Work Several papers (such as =-=[5, 6, 7, 8]-=-) have appeared in literature on the estimation of P&G currents from deterministic input patterns. These methods offer significant improvement in execution times compared to SPICE, while providing acc... |

25 |
Estimation of maximum currents in MOS IC logic circuits
- Chowdury, Barkatullah
- 1990
(Show Context)
Citation Context ...ontact points. Therefore, in the presence of such input dependent and transient current waveforms, we need to define what we mean by the maximum current waveform at a contact point. Chowdhury et. al. =-=[4]-=- find the maximum of the peaks of various transient current waveforms at every contact point for all possible input patterns. They then use these constant peak values at the contact points to redesign... |

18 |
Optimum design of reliable IC power networks having general graph topologies
- Chowdhury
- 1989
(Show Context)
Citation Context ...tied to the buses are called contact points. In VLSI circuits, P&G buses take up an appreciable amount of routing area, typically 20-50% or even more in some circuits. Several design methods, such as =-=[2, 3]-=-, have appeared in literature that make use of the maximum current estimates at the contact points to redesign the buses. The output of a design optimization procedure, however, depends upon the accur... |

11 |
Hercules: A power analyzer of MOS VLSI circuits
- TYAGI
- 1987
(Show Context)
Citation Context ...expensive to handle large VLSI circuits. For these circuits, near linear algorithms rather than exponential, are necessary. Therefore, pattern independent algorithms become a natural choice. Hercules =-=[10]-=- was an initial attempt in the direction of a pattern independent approach to maximum current estimation. However, the analysis presented in [10] makes several simplifying assumptions. The approach su... |

9 |
Automatic sizing of power/ground (P/G) networks VLSI
- Dutta, Marek-Sadowska
- 1989
(Show Context)
Citation Context ...tied to the buses are called contact points. In VLSI circuits, P&G buses take up an appreciable amount of routing area, typically 20-50% or even more in some circuits. Several design methods, such as =-=[2, 3]-=-, have appeared in literature that make use of the maximum current estimates at the contact points to redesign the buses. The output of a design optimization procedure, however, depends upon the accur... |

7 |
SIMCURRENT-An efficient program for the estimation of the current flow of complex CMOS circuits
- Jagau
- 1988
(Show Context)
Citation Context ... along with extensive experimental results on several benchmark circuits. Finally, in section 9, conclusions and some guidelines for future work are presented. 2 Previous Work Several papers (such as =-=[5, 6, 7, 8]-=-) have appeared in literature on the estimation of P&G currents from deterministic input patterns. These methods offer significant improvement in execution times compared to SPICE, while providing acc... |

7 |
Bounds on signal delay in RC mesh networks
- Chan, Schlag
- 1989
(Show Context)
Citation Context ...the case of a resistive network. Equation (11) can be written as V = RI (13) where R is the resistance matrix of the network. The lemma follows from the fact that R is an element-wise positive matrix =-=[21]-=-. For the case of the RC network, the current voltage equation for the system is given by Eq. (12): C V (t) = I(t) \Gamma Y V (t) V (0) = 0 (14) where time zero is taken as the power on time for the c... |

6 |
Power estimation tool for sub-micron cmos vlsi circuit,” European Design Automation Conference
- Rouatbi, Haroun, et al.
- 1992
(Show Context)
Citation Context ... along with extensive experimental results on several benchmark circuits. Finally, in section 9, conclusions and some guidelines for future work are presented. 2 Previous Work Several papers (such as =-=[5, 6, 7, 8]-=-) have appeared in literature on the estimation of P&G currents from deterministic input patterns. These methods offer significant improvement in execution times compared to SPICE, while providing acc... |

6 | Improved Delay and Current Models for Estimating Maximum Currents
- Kriplani, Najm, et al.
- 1994
(Show Context)
Citation Context ... inputs and output. This work, as well as the extension of the proposed algorithms under more general delay and current models is the subject of another paper and the interested reader is referred to =-=[11, 12]-=-. In this paper, due to space limitations, we focus on the algorithmic aspect of the maximum current estimation process under these simplified gate models. Given the specific clocking scheme of the sy... |

6 | Worst case voltage drops in power and ground busses of CMOS VLSI circuits
- Kriplani
- 1993
(Show Context)
Citation Context ... inputs and output. This work, as well as the extension of the proposed algorithms under more general delay and current models is the subject of another paper and the interested reader is referred to =-=[11, 12]-=-. In this paper, due to space limitations, we focus on the algorithmic aspect of the maximum current estimation process under these simplified gate models. Given the specific clocking scheme of the sy... |

6 |
SIMCURRENT - An E cient Program for the Estimation of the Current Flow of Complex CMOS Circuits
- Jagau
- 1990
(Show Context)
Citation Context ...along with extensive experimental results on several benchmark circuits. Finally, in section 9, conclusions and some guidelines for future work are presented. 3s2 Previous Work Several papers (such as=-=[5,6,7,8]-=-) have appeared in literature on the estimation of P&G currents from deterministic input patterns. These methods o er signi cant improvement in execution times compared to SPICE, while providing accep... |

3 |
Delay and bus current evaluation in CMOS logic circuits
- Nabavi-Lishi, Rumin
- 1992
(Show Context)
Citation Context |

1 |
Current density calculation using rectilinear region splitting algorithm for very large scale integration metal migration analysis
- Cha
- 1990
(Show Context)
Citation Context ... drops occurring at various nodes in the power or ground bus, we have to extract the equivalent resistive or RC network of the bus. Various circuit extraction algorithms, such as the one described in =-=[20]-=-, can be used for this purpose. In the RC network, capacitances are assumed to be lumped between various nodes and ground. No floating capacitors are allowed in this formulation. Let's assume that the... |

1 |
Bounds on signal delay inRC mesh networks
- Chan, Schlag
- 1989
(Show Context)
Citation Context ...the case of a resistive network. Equation (11) can be written as V = RI (13) where R is the resistance matrix of the network. The lemma follows from the fact that R is an element-wise positive matrix =-=[21]-=-. For the case of the RC network, the current voltage equation for the system is given by Eq. (12): C _ V (t) = I(t), YV(t) V(0) = 0 (14) where time zero is taken as the power on time for the circuit ... |