Abstract

We apply mathematical logic to a number of problems arising in very large scale integration (VLSI) design automation. The first stage of this dissertation is concerned with techniques for the efficient verification of digital systems. We introduce heuristics based on Binary Decision Diagrams for efficiently representing designs specified as gate-level circuits. We also present an approach to verifying hierarchical designs which uses novel notions of state equivalence to simplify components. The second stage addresses the problem of synthesizing digital designs. We use the logic S1S to demonstrate that the flexibility available for optimizing components in hierarchical designs can be characterized by a finite state automaton. This approach is extended to the problem of synthesizing p...

Citations