Abstract

This paper presents a methodology for concurrently optimizing an IC fabrication process and a standard cell library in order to maximize overall yield. The approach uses the Concurrent Subspace Optimization (CSSO) algorithm, which has been developed for general coupled, multidisciplinary optimization problems. An example is provided showing the application of the algorithm to optimizing a mixed analog-digital library on a CMOS process. 1 Introduction In order to develop high-performance, integrated systems, IC designers are reliant upon having highperformance cell libraries. The development, characterization, and optimization of cell libraries is itself a very complex task, requiring the coordinated efforts of circuit designers and fabrication process engineers. While circuit designers may optimize the performance of individual cells by adjusting device geometries, they do so under the constraints of a fixed fabrication process. One of the key responsibilities of the fabrication proce...

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