Abstract

A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics substantially reducing the computational complexity of robust graph algorithms. The solution found minimizes a cost function accounting for parasitic control and routability considerations. Combined with sensitivity analysis and automatic constraint generation, this algorithm provides a suitable performance-driven approach to analog layout module generation. Examples are reported showing the effectiveness of our approach. 1. INTRODUCTION In recent years, several approaches to the automatic synthesis of analog integrated circuits have been proposed [1, 2, 3]. Significant efforts have been made toward a consistent performance-driven methodology [4], such that the respect of high-level specifications is guaranteed in all design stages. However, a severe discontinuity is pr...

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