## Behavioral Level Power Estimation and Exploration (1994)

Venue: | in Proc. Int. Wkshp. Low Power Design |

Citations: | 61 - 8 self |

### BibTeX

@INPROCEEDINGS{Mehra94behaviorallevel,

author = {Renu Mehra and Jan Rabaey},

title = {Behavioral Level Power Estimation and Exploration},

booktitle = {in Proc. Int. Wkshp. Low Power Design},

year = {1994},

pages = {197--202}

}

### OpenURL

### Abstract

: This paper addresses the problem of estimating, from a behavioral level description, the power consumed by a design. We propose a combination of analytical and stochastic estimation techniques and present comparisons with an architectural level power estimation tool. Average errors of about 20% have been obtained. Based on these estimates, an exploration tool, Explore, has been built to quickly scan the design space and provide estimates of performance metrics such as area and power as guidelines for selection of computational structures and high level design parameters. 1. Introduction High level synthesis has aroused considerable interest in the recent years. While a lot of effort has been put into synthesis for speed and area, power optimization has been explored only recently. Estimation of power consumption of a design is the first step towards integrating power minimization techniques into any synthesis system. Work on power estimation has been done at several different level...

### Citations

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SPICE2: a computer program to simulate semiconductor circuits
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(Show Context)
Citation Context ...cification time. 2. Previous work Increased interest in low power designs has stimulated a lot of research activity in the area of power estimation. Traditionally, circuit level simulators like SPICE =-=[Nag75]-=- and IRSIM [Sal89] have been used for power estimation. Ghosh et. al [Gho92] have addressed this problem at the logic level. Powell [Pow89] suggested characterization of library modules for power esti... |

108 | Fast prototyping of data path intensive architectures - Rabaey, Chu, et al. - 1991 |

73 |
Estimation of Average Switching Activity
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(Show Context)
Citation Context ...s stimulated a lot of research activity in the area of power estimation. Traditionally, circuit level simulators like SPICE [Nag75] and IRSIM [Sal89] have been used for power estimation. Ghosh et. al =-=[Gho92]-=- have addressed this problem at the logic level. Powell [Pow89] suggested characterization of library modules for power estimation using uniform white noise inputs, an approach that is very useful for... |

58 |
IRSIM: An incremental MOS switch-level simulator
- Salz, Horowitz
- 1989
(Show Context)
Citation Context .... Previous work Increased interest in low power designs has stimulated a lot of research activity in the area of power estimation. Traditionally, circuit level simulators like SPICE [Nag75] and IRSIM =-=[Sal89]-=- have been used for power estimation. Ghosh et. al [Gho92] have addressed this problem at the logic level. Powell [Pow89] suggested characterization of library modules for power estimation using unifo... |

47 |
Power estimation for high level synthesis
- Landman, Rabaey
- 1993
(Show Context)
Citation Context ...t the logic level. Powell [Pow89] suggested characterization of library modules for power estimation using uniform white noise inputs, an approach that is very useful for library based tools. Landman =-=[Lan93]-=- describes a more accurate model for module characterization using signal statistics. All these methods, however, analyze power at architectural or lower levels. Recently, there has been an interest i... |

43 | Black-box capacitance models for architectural power analysis - Landman, Rabaey - 1994 |

19 | Estimating Power Dissipation of - Powell, Chau - 1990 |

12 |
Complexity estimation for real time application specific circuits
- Rabaey, Potkonjak
- 1991
(Show Context)
Citation Context ... and worst case errors of 16.6, 14.0, 43.5% respectively. However the values of A act and N bus are known only after final allocation. Estimated minimum bounds on execution units, registers and buses =-=[Rab91b]-=- are used instead, and the model is scaled up by a constant factor. After this simplifying assumption the average and worst case errors increase to 42.6 and 96.1% respectively. After determining the a... |

6 |
HYPER-LP: A System for Power Minimization Using Architectural Transformation
- al
- 1992
(Show Context)
Citation Context ...interest in using behavioral level transformations to minimize power consumption [Cha93]. Despite avid interest in the area, there has been little work in power prediction at that level. Chandrakasan =-=[Cha92]-=- proposed a simplified model for power estimation of some of the components at the behavioral level. 3. Power estimation/prediction The power consumed by general hardware resource is given by (EQ 1) w... |

5 |
Optimizing power using transformations
- al
- 1995
(Show Context)
Citation Context ...al statistics. All these methods, however, analyze power at architectural or lower levels. Recently, there has been an interest in using behavioral level transformations to minimize power consumption =-=[Cha93]-=-. Despite avid interest in the area, there has been little work in power prediction at that level. Chandrakasan [Cha92] proposed a simplified model for power estimation of some of the components at th... |

2 |
personal communications
- Lidsky
(Show Context)
Citation Context ...ison (often used in vector quantization) are compared. The two algorithms for comparing the mean squared distance of a vector X from two vectors C a and C b (constants) are given by Equations 7 and 8 =-=[Lid94]-=-. (EQ 7) (EQ 8) The energy vs. Vdd curves of the two algorithms are shown in Figure 8. The first algorithm has 16 multiply, 14 add, and 17 subtract operations whereas the second one has 8 multiply and... |