## An Architecture for Low-Power Real Time Image Analysis Using 3D Silicon Technology (1998)

Venue: | In Proc. SPIE AeroSense Symp |

Citations: | 2 - 0 self |

### BibTeX

@INPROCEEDINGS{McIlrath98anarchitecture,

author = {Lisa G. McIlrath and Paul M. Zavracky},

title = {An Architecture for Low-Power Real Time Image Analysis Using 3D Silicon Technology},

booktitle = {In Proc. SPIE AeroSense Symp},

year = {1998}

}

### OpenURL

### Abstract

The technology to build highly integrated 3-dimensional computational image sensors by stacking and interconnecting layers of 2-dimensional silicon ICs is being developed. Unlike multi-chip module (MCM-V) packaging, in which interconnect lines are brought to the periphery of a chip stack to achieve vertical integration, this new technology allows virtually unrestricted placement of vertical vias within the interior of the chip. The goal of this development is to enable high speed, high resolution image processing in compact low power wearable systems that would be coupled with a head-mounted display (HMD). Potential applications for these systems include target tracking and image stabilization. In this talk we focus on the architecture of the 3D image sensor, which includes pixel-parallel analog-to-digital conversion and programmable digital processors for pixel and block operations. We show that 3D technology will allow at least an order of magnitude decrease in power dissipation over...

### Citations

689 | Analog VLSI and Neural Systems - Mead - 1989 |

36 |
A 10 b, 20 Msample/s, 35 mW, pipeline A/D converter
- Cho, Gray
- 1995
(Show Context)
Citation Context ...tion error at step i. If the sequence y i is optimally filtered and decimated down to the Nyquist rate, 2f 0 , of the input the remaining in-band noise is given by n 0 (dB) = e + 5:2 \Gamma 9 log 2 N =-=(2)-=- where N is the oversampling ratio, N = (2f 0 T ) \Gamma1 , and e is the root mean square quantization error from the loop A/D. This equation implies that one can ideally obtain 1.5 bits of resolution... |

32 | Decimation for Sigma Delta Modulation - Candy - 1986 |

31 | A CMOS area image sensor with pixel-level - Fowler, Gamal, et al. - 1994 |

30 | The Structure of Quantization Noise from Sigma-Delta Modulation - Candy, Benjamin - 1981 |

19 | Resistive Fuses: Analog Hardware for Detecting Discontinuities in Early Vision - Harris, Koch, et al. - 1989 |

15 | On-Focal-Plane Signal Processing for Current-Mode Active Pixel Sensors
- Nakamura
- 1997
(Show Context)
Citation Context ...ed in image processing. Given an M \Theta M search area with pixels s i;j and an N \Theta N template with pixels b i;j , the best match is found from min k;l N X i=0 N X j=0 jb i;j \Gamma s i+k;j+l j =-=(6)-=- which requires O(M 2 N 2 ) additions. As an alternative to performing this summation for each offset (k; l) of the template in the search window, one can also compute for each b i;j the value d k;l =... |

13 |
A 1.5V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter
- Abo, Gray
- 1999
(Show Context)
Citation Context ...he sampled input data at time t = iT , T being the sampling period, and y i representing the binary-valued output of the modulator, it is easily shown that 18 y i = x i\Gamma1 + e i \Gamma e i\Gamma1 =-=(1)-=- where e i is the quantization error at step i. If the sequence y i is optimally filtered and decimated down to the Nyquist rate, 2f 0 , of the input the remaining in-band noise is given by n 0 (dB) =... |

13 | CMOS resistive fuses for image smoothing and segmentation - Yu, Decker, et al. - 1992 |

9 | E.R.Fossum “CMOS Active Pixel Sensor with On-Chip Successive Approximation Analog-To-Digital Converter
- Zhou
- 1997
(Show Context)
Citation Context ...ce any linear operator L(\Delta) commutes with the average, the operator can be applied directly to the bit stream before averaging. In other words, L(y) = L / 1 N N X i=1 y i ! = 1 N N X i=1 L(y i ) =-=(5)-=- Examples of some basic pixel operations are: ffl Spatial differencing: This is required for edge detection or gradient calculation. To compute the difference between two neighboring pixels, the outpu... |

8 |
A 256×256 CMOS Active Pixel Image Sensor with Motion Detection,” ISSCC Dig
- Dickinson
- 1995
(Show Context)
Citation Context ...unter, as shown in Figure 5, the bus capacitance is divided among the number of rows that can be read in parallel. In other words: P dyn;3D = C bus \Delta BR \Delta N rows \Delta N cols NP \Delta V 2 =-=(8)-=- where NP is the number of rows read simultaneously. If the bus capacitances were the same for the 2D and 3D arrays, the dynamic power in the 3D array would be over an order of magnitude less than tha... |

7 | A CCD/CMOS-Based Imager with Integrated Focal Plane Signal Processing - Keast, Sodini - 1993 |

6 |
CMOS active pixel sensor array with programmable multiresolution readout,” presented at 1995
- Kemeny, Pain, et al.
- 1995
(Show Context)
Citation Context ...put busses. In a 2D implementation, each cell must drive a bit onto the column bus and to an output pad driver. The power required is P dyn;2D = C bus \Delta BR \Delta N rows \Delta N cols \Delta V 2 =-=(7)-=- where BR is the output bit rate of the cell, BR = N \Delta F , N being the oversampling ratio and F being the frame rate. In this equation, we neglect the dynamic power due to driving control lines Q... |

6 | An analog VLSI chip for estimating the focus of expansion
- McQuirk
- 1996
(Show Context)
Citation Context ...e maximum photocurrent and the difference in the reference levels V high and V low . The minimum time for the modulator to complete an integration cycle is �� min = C pix (V high \Gamma V low ) I =-=max (9) and-=- the corresponding frame rate is F = 1 N��min (10) where N is the oversampling rate. Figure 11 plots the normalized dynamic power (V = 1), from equation (8), and frame rate vs. V high \Gamma V low... |

5 | Temes, "Oversampling methods for a/d and d/a conversion - Candy, C - 1992 |

4 | A CCD/CMOS focal-plane array edge detection processor implementing the multiscale veto algorithm - McIlrath - 1996 |

4 | Abacus: A Reconfigurable Bit-Parallel Architecture for Early Vision - Bolotski - 1996 |

3 | An Integrated Computing Structure for Pixel-Parallel Image Processing - Gealow - 1997 |

2 |
On sensor video compression
- Aizawa, Ohno, et al.
- 1995
(Show Context)
Citation Context ...rence levels V high and V low . The minimum time for the modulator to complete an integration cycle is �� min = C pix (V high \Gamma V low ) I max (9) and the corresponding frame rate is F = 1 N��=-=��min (10)-=- where N is the oversampling rate. Figure 11 plots the normalized dynamic power (V = 1), from equation (8), and frame rate vs. V high \Gamma V low for a 256\Theta256 array assuming C pix = 50fF, C bus... |

1 |
An addressable 256\Theta256 photodiode image sensor array with an 8-bit digital output
- Jansson, Inglehag, et al.
- 1993
(Show Context)
Citation Context ... on-chip. An easy lowpass filter/decimator circuit to build is a simple counter. If equation (1) is averaged over N steps, one obtains y = 1 N N X i=1 y i = 1 N N \Gamma1 X i=0 x i + e N \Gamma e 0 N =-=(3)-=- giving an net rms quantization noise of n 0;avg (dB) = e + 3:0 \Gamma 6 log 2 N (4) or an increase of 1 bit of resolution for every doubling of N . 19 The oversampling rate must be higher for the sam... |

1 |
On-focal-plane ADC: Recent progress at JPL
- Panicacci, Mansoorian, et al.
(Show Context)
Citation Context ...equation (1) is averaged over N steps, one obtains y = 1 N N X i=1 y i = 1 N N \Gamma1 X i=0 x i + e N \Gamma e 0 N (3) giving an net rms quantization noise of n 0;avg (dB) = e + 3:0 \Gamma 6 log 2 N =-=(4)-=- or an increase of 1 bit of resolution for every doubling of N . 19 The oversampling rate must be higher for the same resolution, but the gain in circuit simplicity is significant. Figure 5. Structure... |

1 | Gamal, "A 128\Theta128 pixel CMOS area image sensor with multiplexed pixel level A/D conversion - Yang, Fowler, et al. - 1996 |