Abstract

* Existing approaches to data path allocation in highlevel synthesis use a binding model in which values are assigned to the same register for their entire lifetimes. This paper describes an extended binding model in which segments of a value's lifetime may reside in different registers if there is a cost advantage in doing so. In addition, the model supports multiple copies of values and the use of functional units to "pass through" unmodified values to reduce interconnect. This model is exploited in an allocation tool that uses iterative improvement to search for low-cost designs. Results show that allocation costs can be substantially reduced using this model. 1. Introduction Data path allocation [1] is the problem of assigning hardware to a scheduled control/data flow graph (CDFG) to implement a specified behavior while meeting performance and timing constraints and minimizing implementation cost. The CDFG specifies operators that manipulate data, data values that require storage, ...

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