Abstract

) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design and Fault Tolerance (Prof. Dr. ##. Schmid) P.O. Box 6980, W-7500 Karlsruhe, Germany 1. INTRODUCTION The use of higher-order logic and an associated interactive theorem proving environment for hardware verification has established itself as an important technique for formal hardware validation [CaGM 86, FFFH 89]. In spite of the fact that such techniques are powerful and can be used for validation of complex systems, they continue to remain purely within the purview of theorem proving specialists. The only way to bring such a system closer to circuit designers is to augment the degree of automation and provide a camouflaged environment which mirrors the designer's view of hardware. The first step in this direction is to automate the proofs of all first-order and simple higher-order statements, within such systems, which has been achieved by the tool FAUST [KuKS 91, ScKK 91a]. Further aut...

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