## Rate Analysis for Embedded Systems (1998)

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Venue: | ACM Trans. on Design Automation of Electronic Systems |

Citations: | 37 - 11 self |

### BibTeX

@ARTICLE{Mathur98rateanalysis,

author = {Anmol Mathur and Ali Dasdan and Rajesh K. Gupta},

title = {Rate Analysis for Embedded Systems},

journal = {ACM Trans. on Design Automation of Electronic Systems},

year = {1998},

volume = {3}

}

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### Abstract

ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept, ACM Inc., 1515 Broadway, New York, NY 10036 USA, fax +1 (212) 869-0481, or permissions@acm.org Rate Analysis for Embedded Systems Anmol Mathur Ali Dasdan Rajesh K. Gupta y Department of Computer Science University of Illinois at Urbana-Champaign Urbana, IL 61801 September 3, 1997 Abstract. Embedded systems consist of interacting components that are required to deliver a specific functionality under constraints on execution rates and relative time separation of the components. In this paper, we model an embedded system using concurrent processes interacting through synchronization. We assume that there are rate constraints on the execution rates of processes imposed by the designer or the environment of the system, where ...

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A characterization of the minimum cycle mean in a digraph
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Citation Context ...ate Analysis : Single SCC Using the result in Theorem 1, we need to compute the maximum mean cycle delay to compute the average execution rate of processes in a SCC. The following theorem due to Karp =-=[8]-=- allows the design of an efficient algorithm for finding the maximum mean cycle delay. Its proof can be found in [1] (page 47). Theorem 3. Consider a strongly connected graph G(V; E) with n nodes. Let... |

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Citation Context ...raph, and consequently their delay does not affect any execution rates. Let us now consider the steps involved in the rate analysis of the process graph in Fig. 6. p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 9 =-=[2, 6]-=- [4, 20] [3, 10] [9, 18] [10, 20] [1, 4] [4, 10] [3, 5] [3, 6] [7,20] [5, 8] SCC 1 SCC 2 Figure 6: Process graph used in Example 4.1 For SCC 1 : For computing r l , set all the edge delays to their up... |

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Citation Context ...bles the execution of process p j by sending an enable signal to process p j . Each edge, (p i ; p j ), in the process graph is associated with a delay interval \Delta ij = (d ij ; D ij ) that [2, 3] =-=[1, 4]-=- p 2 p 1 Figure 2: A process graph with two processes. bounds the time after the initiation of an execution of process p i when p j receives the enable signal from p i . Let ffi ij be the actual delay... |

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Citation Context ...s not valid if an embedded system software is implemented as a set of co-routines where each co-routine consists of an initial process that is executed only once and a repeating body. Hulgaard et al. =-=[7]-=- have addressed the problem of finding tight bounds on the time interval between events in a process graph using implicit unfolding of the process graph. These bounds can be converted to bounds on the... |

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Performance evaluation of concurrent systems using petri nets
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Citation Context ... their algorithms require the processes to be implemented only in a non-pipelined manner. Rate analysis has also been studied for asynchronous, concurrent systems modeled using timed Petri nets [2] , =-=[9]-=-, [12]. However, their analysis is based on restrictive assumptions, such as the vector of start times for the processes is a specially chosen vector. This assumption is not valid if an embedded syste... |

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Citation Context ...ssues an enable signal for another process, and the estimation of the communication delay between the process generating the enable signal and the one receiving it. This problem has been addressed by =-=[5]-=-, [10] and is not the focus of this paper. 2. Consistency Checking of Rate Constraints: This problem arises because the designer usually specifies the rate constraints independently for each process. ... |

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Citation Context ...1: Interaction between rate analysis and synthesis in the design of an embedded system. The problem of determining execution rates has been studied in several different contexts. Gupta and De Micheli =-=[6]-=- have examined the problem of rate analysis in embedded systems, but they consider very limited interaction/synchronization between the component processes. Further, their algorithms require the proce... |

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Speci cation and Analysis of Timing Constraints for Embedded Systems
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Citation Context ... 1: Interaction between rate analysis and synthesis in the design of an embedded system. The problem of determining execution rates has been studied in several di erent contexts. Gupta and De Micheli =-=[6]-=- have examined the problem of rate analysis in embedded systems, but they consider very limited interaction/synchronization between the component processes. Further, their algorithms require the proce... |

2 |
Performance Analysis of Data-Driven Networks
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- 1989
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Citation Context ...ate constraints 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 C2 C3 C4 C5 C1 C0 [3,4] [5,8] [2,23] [1,2] [2,3] [12,20] [4,13] [10,15] [4,6] [4,6] [3,5] [3,5] [4,6] [10,17] [2,3] [2,4] [2,5] [2,6] [2,7] =-=[3,11]-=- [2,10] [5,15] [8,20] [5,16] [7,18] Figure 8: The process graph used in Example 6.1. are consistent, and the constraint interval for C4 is [0:05; 0:10] (this is the intersection of the constraint inte... |

1 |
Scheduling Parallel
- Reiter
- 1968
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Citation Context ...ing theorem establishes that our definition of execution rate in Eq. 2 is well defined, and can be related to the maximum mean cycle in the process graph. Weaker forms of this theorem can be found in =-=[1, 2, 12, 13]-=-. Theorem 1. Consider a strongly connected process graph and let x i (k), ks0 be the sequence of time instances at which process p i executes. Then there exists some Ns0 such that the following are tr... |