## Zero-Skew Clock Routing Trees With Minimum Wirelength (1992)

Venue: | Proc. IEEE Intl. Conf. on ASIC |

Citations: | 49 - 13 self |

### BibTeX

@INPROCEEDINGS{Boese92zero-skewclock,

author = {Kenneth Boese and Andrew B. Kahng},

title = {Zero-Skew Clock Routing Trees With Minimum Wirelength},

booktitle = {Proc. IEEE Intl. Conf. on ASIC},

year = {1992},

pages = {1--1}

}

### Years of Citing Articles

### OpenURL

### Abstract

In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we present the Deferred-Merge Embedding (DME) algorithm, which in linear time embeds any given connection topology into the Manhattan plane to create a clock tree with zero skew while minimizing total wirelength. Extensive experimental results show that the algorithm yields exact zero skew trees with 9% to 16% wirelength reduction over previous constructions [5] [6]. The DME algorithm may be applied to either the Elmore or the linear delay model, and yields optimal total wirelength for linear delay. 1 Introduction In synchronous VLSI designs, circuit speed is increasingly limited by clock skew, which is the maximum difference in arrival times of the clocking signal ...

### Citations

433 |
Circuits, Interconnections, and Packaging for VLSI
- Bakoglu
- 1990
(Show Context)
Citation Context ...is the maximum difference in arrival times of the clocking signal at the synchronizing elements. This is seen from the following well-known inequality governing the clock period of a clock signal net =-=[1]-=- [5]: clock periodst d + t skew + t su + t ds where t d is the delay on the longest path through combinational logic, t skew is the clock skew, t su is the set up time of the synchronizing elements, a... |

180 | Signal delay in RC tree networks - Rubinstein, eld, et al. - 1983 |

73 | Zero skew clock routing with minimum wirelength
- Chao, Hsu, et al.
- 1992
(Show Context)
Citation Context ...h topology G and sinks S. DME also produces the optimal ZST in the variation of the Zero Skew Clock Routing Problem where the position of the source is fixed. This extension to Theorem 1 is proved in =-=[4]-=-. Under the linear model, DME also minimizes the source-sink delay in a ZST. We now prove that given any input topology, DME will in fact construct a ZST with delay equal to one-half the diameter of t... |

61 |
Exact zero skew
- Tsay
- 1991
(Show Context)
Citation Context ...in the synchronizing elements. With increased switching speeds, t skew may account for over 10% of the system cycle time in highperformance systems [1]. Previous methods for skew minimization [5] [6] =-=[8]-=- concentrate on the problem of computing a clock tree topology, and only incompletely address the associated problem of finding a minimum-cost embedding of the topology. However, the total wirelength ... |

49 |
J.M.: Zero skew clock net routing
- Chao, Hsu, et al.
- 1992
(Show Context)
Citation Context ...y and optimal source-sink delay overall. 8 Remarks and Acknowledgements Most of the results in this paper also appear in [4], reflecting a collaboration between the present authors and the authors of =-=[3]-=- that arose after it was learned that the two groups had, through independent research, come up with essentially the same embedding approach. The authors are grateful to Dr. Ren-Song Tsay for providin... |

46 |
Clock routing. for high-performance ICs
- Jackson, Srinivasan, et al.
- 1990
(Show Context)
Citation Context ...e with zero skew while minimizing total wirelength. Extensive experimental results show that the algorithm yields exact zero skew trees with 9% to 16% wirelength reduction over previous constructions =-=[5]-=- [6]. The DME algorithm may be applied to either the Elmore or the linear delay model, and yields optimal total wirelength for linear delay. 1 Introduction In synchronous VLSI designs, circuit speed i... |

43 | high-performance clock routing based on recursive geometric matching
- Kahng, Cong, et al.
- 1991
(Show Context)
Citation Context ...ct zero skew, and may thus be applied to previously generated clock trees in order to improve both wirelength and delay. Experiments show that applying DME to topologies generated by the algorithm of =-=[6]-=- results in wirelength reductions of 9% to 16% over [5] [6] [8]. Finally, under the linear delay model, DME yields optimal total wirelength for the topology and optimal source-sink delay overall. 8 Re... |