Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization (1991)
| Venue: | Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS-IV |
| Citations: | 19 - 2 self |
BibTeX
@INPROCEEDINGS{Bhandarkar91performancefrom,
author = {Dileep Bhandarkar and Douglas Clark},
title = {Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization},
booktitle = {Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS-IV},
year = {1991},
pages = {310--319}
}
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Abstract
Performance comparisons across different computer architectures cannot usually separate the architectural contribution from various implementation and technology contributions to performance. This paper compares an example implementation from the RISC and CISC architectural schools (a MIPS M/2000 and a Digital VAX 8700) on nine of the ten SPEC benchmarks. The organizational similarity of these machines provides an opportunity to examine the purely architectural advantages of RISC. The RISC approach offers, compared with VAX, many fewer cycles per instruction but somewhat more instructions per program. Using results from a software monitor on the MIPS machine and a hardware monitor on the VAX, this paper shows that the resulting advantage in cycles per program ranges from slightly under a factor of 2 to almost a factor of 4, with a geometric mean of 2.7. It also demonstrates the correlation between cycles per instruction and relative instruction count. Various reasons for this correlati...
