## Generalized Constraint Generation for Analog Circuit Design (1993)

Venue: | in Proc. IEEE ICCAD |

Citations: | 9 - 5 self |

### BibTeX

@INPROCEEDINGS{Charbon93generalizedconstraint,

author = {Edoardo Charbon and Enrico Malavasi and Alberto Sangiovanni-Vincentelli},

title = {Generalized Constraint Generation for Analog Circuit Design},

booktitle = {in Proc. IEEE ICCAD},

year = {1993},

pages = {408--414}

}

### OpenURL

### Abstract

A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from highlevel performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graph-based techniques to extract the necessary geometric information. 1 Introduction The design of analog circuits is often a difficult task compared with a digital one of similar complexity because of the higher number of specifications and the importance of second order effects. In addition, the continuously growing complexity of analog integrated circuits has required a better control over the design quality and the redefinition of tasks like module generation and floorplanning. The performances of...

### Citations

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Citation Context ... matched parasitics. 4 Generating Topological Constraints 4.1 Device Matching The importance of device matching in integrated circuits has been shown not only for active but also for passive elements =-=[13, 14]-=-. Designers generally impose matching constraints on circuit devices to ensure that voltage and current mismatches in these devices be bounded. These constraints can be mapped directly onto constraint... |

55 |
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Citation Context ...ram of the constraint generation process is shown in figure 1. From hardware and performance description a sensitivity analysis of the circuit is performed using mixed symbolic / numerical techniques =-=[9, 10]-=-. Using performance sensitivity information and a priori estimates of minimum and maximum parasitic values, the subset of critical parasitics is detected. A quadratic programming approach is then used... |

39 | A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits
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Citation Context ...uch as mixed-signal circuits, this task may become difficult if not impossible, due to the interactions between circuit components and parasitics. During the synthesis of complex mixed-signal systems =-=[8]-=- it is often required to map high-level performance specifications onto several distinct sets of layout constraints. The constraint generation process should therefore be flexible. In this paper a gen... |

20 |
Constraint Generation for Routing Analog Circuits
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Citation Context ...rmance degradation of a circuit due to layout parasitics can be modeled using performance sensitivities [1]. Sensitivities can also be used to generate a set of constraints on interconnect parasitics =-=[2]-=-. Techniques [3, 4, 5, 6, 7] have been proposed for a constraint-based approach to the layout of analog integrated circuits. In these approaches a constraint generator is used to map a set of high-lev... |

19 | A Constraint-Driven Placement Methodology for Analog Integrated Circuits
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Citation Context ...on of a circuit due to layout parasitics can be modeled using performance sensitivities [1]. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [2]. Techniques =-=[3, 4, 5, 6, 7]-=- have been proposed for a constraint-based approach to the layout of analog integrated circuits. In these approaches a constraint generator is used to map a set of high-level performance specification... |

12 |
Constraint-based channel routing for analog and mixed analog/digital circuits
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Citation Context ...on of a circuit due to layout parasitics can be modeled using performance sensitivities [1]. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [2]. Techniques =-=[3, 4, 5, 6, 7]-=- have been proposed for a constraint-based approach to the layout of analog integrated circuits. In these approaches a constraint generator is used to map a set of high-level performance specification... |

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Citation Context ...ram of the constraint generation process is shown in figure 1. From hardware and performance description a sensitivity analysis of the circuit is performed using mixed symbolic / numerical techniques =-=[9, 10]-=-. Using performance sensitivity information and a priori estimates of minimum and maximum parasitic values, the subset of critical parasitics is detected. A quadratic programming approach is then used... |

6 |
A Routing Methodology for Analog Integrated Circuits
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Citation Context ...on of a circuit due to layout parasitics can be modeled using performance sensitivities [1]. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [2]. Techniques =-=[3, 4, 5, 6, 7]-=- have been proposed for a constraint-based approach to the layout of analog integrated circuits. In these approaches a constraint generator is used to map a set of high-level performance specification... |

5 |
Use of Performance Sensitivities in Routing of Analog Circuits
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Citation Context ...ircuit devices, layout induced parasitics increasingly influence the circuit behavior. The performance degradation of a circuit due to layout parasitics can be modeled using performance sensitivities =-=[1]-=-. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [2]. Techniques [3, 4, 5, 6, 7] have been proposed for a constraint-based approach to the layout of analog ... |

4 |
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Citation Context ...y influenced by independent sources. 2.3 Canonical Representation of Performance A generalized expression for the computation of sensitivities from a set of arbitrary performances has been derived in =-=[11, 12]-=-. This formulation has been used by us to represent all performances analyzed in a compact and rigorous way, thus ensuring flexibility of our design tools. For completeness the formulation has been re... |

3 | Performance-driven compaction for analog integrated circuits
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2 | Optimum Stacked Layout for Analog CMOS ICs
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2 |
Performance Optimization of Integrated Circuits", Memorandum UCB/ERL
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(Show Context)
Citation Context ...y influenced by independent sources. 2.3 Canonical Representation of Performance A generalized expression for the computation of sensitivities from a set of arbitrary performances has been derived in =-=[11, 12]-=-. This formulation has been used by us to represent all performances analyzed in a compact and rigorous way, thus ensuring flexibility of our design tools. For completeness the formulation has been re... |

1 |
Technological Considerations for Monolithic MOS SwitchedCapacitor Filtering Systems
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Citation Context ... matched parasitics. 4 Generating Topological Constraints 4.1 Device Matching The importance of device matching in integrated circuits has been shown not only for active but also for passive elements =-=[13, 14]-=-. Designers generally impose matching constraints on circuit devices to ensure that voltage and current mismatches in these devices be bounded. These constraints can be mapped directly onto constraint... |

1 |
Sensitivity Computation in SPICE3", M.s
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Citation Context ...scuss in detail two particularly significant circuits to highlight the features of the proposed algorithms. For the computation of voltage sensitivities, standard analysis methods available in SPICE3 =-=[15]-=- have been used. Performance sensitivities are computed from circuit variable sensitivities using the principles presented in section 2.3. The sensitivity information required for matching and symmetr... |