VHDL Testability Analysis based on Fault Clustering and Implicit Fault Injection
BibTeX
@MISC{Bietti_vhdltestability,
author = {F.S. Bietti and F. Ferrandi and F. Fummi and D. Sciuto and F. Fummi D. Sciuto},
title = {VHDL Testability Analysis based on Fault Clustering and Implicit Fault Injection},
year = {}
}
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Abstract
Testability analysis of VHDL sequential models is the main topic of this paper. We investigate the possibility to obtain information about the testability of a sequential VHDL description before its actual synthesis. The analysis is based on an implicit fault model that injects faults into a BDD based description extracted from the VHDL representation. Such an injection is related to the original VHDL representation thus allowing the identification of potential testability problems before RTL and logic synthesis. Fault injection is performed efficiently by exploiting the concept of fault clustering, that is, the possibility of grouping faults and analyzing them concurrently. The proposed methodology is applied to benchmarks for efficiency evaluation and to a real VHDL description. 1 Introduction Algorithms concerning the testing field are based on models which abstract the behavior of physical defects. Such models include fault models, error models or failure models depending on the ...
