## High-Radix Modular Multiplication for Cryptosystems (1993)

Venue: | 11th IEEE Symposium on Computer Arithmetic |

Citations: | 21 - 4 self |

### BibTeX

@INPROCEEDINGS{Kornerup93high-radixmodular,

author = {Peter Kornerup},

title = {High-Radix Modular Multiplication for Cryptosystems},

booktitle = {11th IEEE Symposium on Computer Arithmetic},

year = {1993},

pages = {277--283},

publisher = {IEEE Computer Society Press}

}

### OpenURL

### Abstract

Two algorithms for modular multiplication with very large moduli are analyzed, in particular for their applicability when a high radix is used for the multiplier. Both algorithms perform modulo reductions interleaved with the addition of partial products, one algorithm is using the standard residue system, whereas the other utilizes a non-standard system employing reductions modulo a power of the base. The emphasis is on situations -- like in cryptosystems -- where modular exponentiation is to be realized by many repeated modular multiplications on very large operands, e.g. for cryptosystems with key lengths of 500-1000 bits. 1 Introduction Modular multiplication is a fundamental operation in the implementation of modular exponentiation as needed in many cryptosystems, e.g. the RSA two-key system [6] and in the recently proposed digital signature standard DSS [3]. In such applications very large moduli are needed to safeguard the information, which makes modular exponentiation a very ...

### Citations

3231 | A Method for Obtaining Digital Signatures and Public-Key Cryptosystems - Rivest, Shamir, et al. - 1978 |

464 |
Modular multiplication without trial division
- Montgomery
- 1985
(Show Context)
Citation Context ...computed from the most significant bits of the accumulator contents. An alternative approach, where modulo reductions are computed from the least significant bits based on an idea by Peter Montgomery =-=[2]-=-, has been reported implemented on a gate-array in [7], also base 2. In this paper we will analyze these two approaches for modular reductions during multiplications, however applied to higher radix i... |

40 |
A survey of hardware implementation of RSA
- Brickell
- 1989
(Show Context)
Citation Context ...lementations are preferable in many applications. There has been a number of publications in recent years reporting on modular exponentiation. A survey of actual hardware implementations was given in =-=[1]-=-, and further designs and implementations have been reported since then. All reported implementations so far have been based on multiplications where accumulated partial products are formed by interpr... |

35 |
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation
- Takagi
- 1992
(Show Context)
Citation Context ... reduce the total number of cycles. Emphasis will be on designs which are suitable for single-chip VLSI implementations of modular exponentiations. A design for radix 4 has recently been presented in =-=[8]-=-, and a radix 32 design, which was presented in [5], is presently being implemented as a single chip prototype for RSA encryption/decryption with 561-bit keys and a projected speed above 64Kbps. Both ... |

23 | Digit-Set Conversion: Generalization and Application
- Kornerup
- 1994
(Show Context)
Citation Context ...ma p + dlog 2 me, hence p = k + 1 \Gamma blog 2 (ff \Gamma 1 2 )c is sufficient to assure j\Deltajs(ff \Gamma 1 2 )2 k m. Since S is in signed-digit binary a subsequent conversion into sign-magnitude =-=[4]-=- is needed for the table look-up. Note that only the magnitude part is needed for the look-up since sign(q i ) = sign(S), thus using the values of ff from (8) we obtain the following sufficient table ... |

21 | Hardware Speedups in Long Integer Multiplication
- Shand, Bertin, et al.
- 1991
(Show Context)
Citation Context ...ator contents. An alternative approach, where modulo reductions are computed from the least significant bits based on an idea by Peter Montgomery [2], has been reported implemented on a gate-array in =-=[7]-=-, also base 2. In this paper we will analyze these two approaches for modular reductions during multiplications, however applied to higher radix implementations to reduce the total number of cycles. E... |

17 |
A New Carry-Free Division Algorithm and its Application to a Single Chip 1024-b RSA Processor
- Vandemeulebroecke, Vanzieledhem
- 1990
(Show Context)
Citation Context ... based on multiplications where accumulated partial products are formed by interpreting the multiplier in base 2. A fairly straightforward such VLSI 1024bit single-chip implementation was reported in =-=[9]-=-, where modulo reductions are based on This work has been supported by the Danish Natural Science Research Council, grant no. 5.21.08.02. To be presented at, and published in proceedings of the 11th I... |

11 |
A high-radix hardware algorithm for calculating the exponential m e modulo n
- Orup, Kornerup
- 1991
(Show Context)
Citation Context ...e on designs which are suitable for single-chip VLSI implementations of modular exponentiations. A design for radix 4 has recently been presented in [8], and a radix 32 design, which was presented in =-=[5]-=-, is presently being implemented as a single chip prototype for RSA encryption/decryption with 561-bit keys and a projected speed above 64Kbps. Both of these designs employ the standard method of modu... |