Instruction-Level Parallelism for Reconfigurable Computing (1998)
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| Venue: | In Proc. International Workshop on Field Programmable Logic |
| Citations: | 24 - 1 self |
BibTeX
@INPROCEEDINGS{Callahan98instruction-levelparallelism,
author = {Timothy J. Callahan and John Wawrzynek},
title = {Instruction-Level Parallelism for Reconfigurable Computing},
booktitle = {In Proc. International Workshop on Field Programmable Logic},
year = {1998},
pages = {248--257},
publisher = {Springer-Verlag}
}
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Abstract
. Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural match for automatic compilation to a reconfigurable coprocessor. This paper will review these techniques in their original context, describe how we have adapted them for reconfigurable computing, and present some preliminary results on compiling application programs written in the C programming language. 1 Introduction In this work we consider compilation for a hybrid reconfigurable computing platform consisting of a microprocessor coupled with field-programmable gate array (FPGA) circuitry used as a reconfigurable accelerator. The FPGA is configured to provide a customized accelerator for compute-intensive tasks. This accel...
