## Towards a High-Level Power Estimation Capability (1996)

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Venue: | IEEE trans. on CAD |

Citations: | 93 - 9 self |

### BibTeX

@ARTICLE{Nemani96towardsa,

author = {Mahadevamurty Nemani and Farid N. Najm},

title = {Towards a High-Level Power Estimation Capability},

journal = {IEEE trans. on CAD},

year = {1996},

volume = {15},

pages = {588--598}

}

### Years of Citing Articles

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### Abstract

We will present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a high-level power estimation capability is required in order to provide early warning of any power problems, before the circuit-level design has been specified. With such early warning, the designer can explore design trade-offs at a higher level of abstraction than previously possible, reducing design time and cost. Our estimator is based on the use of entropy as a measure of the average activity to be expected in the final implementation of a circuit, given only its Boolean functional description. This technique has been implemented and tested on a variety of circuits. The empirical results to be presented are very promising and demonstrate the feasibility and utility of this approach. y This work was supported in part by Intel Corp., Santa Clara, CA. Submitted to the IEEE Transactions on CAD, 1995. 1. Introduction The high device count and operati...

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Citation Context ...mputational work. In 1972, Hellerman [2] proposed the use of entropy as a measure of computational work. Entropy will be discussed at length in the next section. These e orts were mostly unsuccessful =-=[3]-=- for a general computational process, but were reasonably successful [4{8] in the limited context of a combinational logic circuit implementing a Boolean function. Thus, it seems plausible to apply th... |