## Application of Boolean Unification to Combinational Logic Synthesis (1991)

Venue: | in Proceedings of IEEE International Conference on Computer-Aided Design |

Citations: | 12 - 5 self |

### BibTeX

@INPROCEEDINGS{Fujita91applicationof,

author = {Masahiro Fujita and Yutaka Tamiya and Yuji Kukimoto and Kuang-chien Chen},

title = {Application of Boolean Unification to Combinational Logic Synthesis},

booktitle = {in Proceedings of IEEE International Conference on Computer-Aided Design},

year = {1991},

pages = {510--513}

}

### OpenURL

### Abstract

Boolean unification is an algorithm to obtain the general solution of a given Boolean equation. Since the general solution provides a way to represent complete don't care sets in a functional form, Boolean unification can be a powerful method when applied to logic synthesis. In this paper we present various applications of Boolean unification to combinational logic synthesis. Three topics of combinational logic synthesis: redesign, multi-level logic minimization and minimization of Boolean relations are discussed. All these problems can be uniformly formalized as Boolean unification problems. Experimental results are also reported. 1 Introduction Boolean Unification[9, 8] is a procedure to obtain the general solution of a given Boolean equation or formula. In the field of CAD for integrated circuit design, it has been applied to logic verification and test pattern generation [11, 4] combined with logic programming. In this paper we present various applications of Boolean unification...

### Citations

2930 | Graph-based algorithms for Boolean function manipulation
- Bryant
- 1986
(Show Context)
Citation Context ...le us to explore larger design space. In section 2, we briefly review a Boolean unification problem and its algorithm and show that the algorithm can be easily implemented by Binary Decision Diagrams =-=[3]-=-. In section 3, we present three applications of Boolean unification to combinational logic synthesis and show how to formalize them in a unified framework. A method to synthesize circuits from the ge... |

121 |
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation
- Minato, Ishiura, et al.
- 1990
(Show Context)
Citation Context ...ication are used as permissible functions [10]. The details can be found in a forthcoming paper. 5 Implementation and Results We have implemented Boole's method using shared BDD's with negative edges =-=[7]-=- on Sparc station 2. As the variable ordering of BDD's, we select variables to be unified(p i ) first followed by non-unified variables(q i ). A case splitting variable in figure 1 is selected in the ... |

43 |
Minimization of Boolean Relations
- Brayton, Somenzi
(Show Context)
Citation Context ...In this paper we present various applications of Boolean unification to combinational logic synthesis. Three topics: redesign [5], multi-level logic minimization and minimization of Boolean relations =-=[12]-=- are discussed. All these problems can be uniformly formalized as Boolean unification problems. The general solutions of these problems can be obtained by using Boolean unification algorithms [9, 8]. ... |

39 |
Embedding Boolean Expressions into Logic Programming
- Buttner, Simonis
- 1987
(Show Context)
Citation Context ...ocedure to obtain the general solution of a given Boolean equation or formula. In the field of CAD for integrated circuit design, it has been applied to logic verification and test pattern generation =-=[11, 4]-=- combined with logic programming. In this paper we present various applications of Boolean unification to combinational logic synthesis. Three topics: redesign [5], multi-level logic minimization and ... |

39 |
The transduction method - design of logic networks based on permissible functions
- Muroga, Kambayashi, et al.
- 1989
(Show Context)
Citation Context ... the circuit2. 3.2 Multi-level Logic Minimization A general solution of a given equation obtained by Boolean unification can represent don't care sets in much broader sense than those proposed so far =-=[10, 2, 1]-=-. Don't care sets used in logic synthesis methods in [10, 2, 1] are basically defined for a single net or gate, and only one logic function corresponding to a net can be modified at the same time duri... |

28 |
Boolean Unification – The story so far
- Martin, Nipkow
- 1989
(Show Context)
Citation Context ...imization of Boolean relations are discussed. All these problems can be uniformly formalized as Boolean unification problems. Experimental results are also reported. 1 Introduction Boolean Unification=-=[9, 8]-=- is a procedure to obtain the general solution of a given Boolean equation or formula. In the field of CAD for integrated circuit design, it has been applied to logic verification and test pattern gen... |

21 |
Test Generation using the Constraint Logic Programming Language CHIP
- Simonis
- 1989
(Show Context)
Citation Context ...ocedure to obtain the general solution of a given Boolean equation or formula. In the field of CAD for integrated circuit design, it has been applied to logic verification and test pattern generation =-=[11, 4]-=- combined with logic programming. In this paper we present various applications of Boolean unification to combinational logic synthesis. Three topics: redesign [5], multi-level logic minimization and ... |

16 |
Unification in Boolean Rings
- Martin, Nipkow
- 1988
(Show Context)
Citation Context ...imization of Boolean relations are discussed. All these problems can be uniformly formalized as Boolean unification problems. Experimental results are also reported. 1 Introduction Boolean Unification=-=[9, 8]-=- is a procedure to obtain the general solution of a given Boolean equation or formula. In the field of CAD for integrated circuit design, it has been applied to logic verification and test pattern gen... |

9 |
Redesign and automatic error correction of combinational circuits
- Fujita, Kakuda, et al.
- 1991
(Show Context)
Citation Context ...tion and test pattern generation [11, 4] combined with logic programming. In this paper we present various applications of Boolean unification to combinational logic synthesis. Three topics: redesign =-=[5]-=-, multi-level logic minimization and minimization of Boolean relations [12] are discussed. All these problems can be uniformly formalized as Boolean unification problems. The general solutions of thes... |

8 |
Bold: The boulder optimal logic design system
- Hachtel, Lightner, et al.
- 1988
(Show Context)
Citation Context ... the circuit2. 3.2 Multi-level Logic Minimization A general solution of a given equation obtained by Boolean unification can represent don't care sets in much broader sense than those proposed so far =-=[10, 2, 1]-=-. Don't care sets used in logic synthesis methods in [10, 2, 1] are basically defined for a single net or gate, and only one logic function corresponding to a net can be modified at the same time duri... |

8 |
Eang, “Mis: A multiple-level interactive logic optimization system
- Brayton, Rudell, et al.
- 1987
(Show Context)
Citation Context ... the circuit2. 3.2 Multi-level Logic Minimization A general solution of a given equation obtained by Boolean unification can represent don't care sets in much broader sense than those proposed so far =-=[10, 2, 1]-=-. Don't care sets used in logic synthesis methods in [10, 2, 1] are basically defined for a single net or gate, and only one logic function corresponding to a net can be modified at the same time duri... |

4 |
Heuristic minimization of boolean relations using testing techniques
- Ghosh, Devadas, et al.
- 1990
(Show Context)
Citation Context ...elations are the generalizations of incompletely specified functions and arise in many applications [12]. There are several approaches to the minimization of Boolean relations in sum-of-product forms =-=[12, 6, 13]-=-, but no methods for multi-level minimization of Boolean relations have been published so far. Here we present how to apply Boolean unification to the multilevel minimization of Boolean relations. Sin... |