Application of Boolean Unification to Combinational Logic Synthesis (1991)
| Venue: | in Proceedings of IEEE International Conference on Computer-Aided Design |
| Citations: | 11 - 5 self |
BibTeX
@INPROCEEDINGS{Fujita91applicationof,
author = {Masahiro Fujita and Yutaka Tamiya and Yuji Kukimoto and Kuang-chien Chen},
title = {Application of Boolean Unification to Combinational Logic Synthesis},
booktitle = {in Proceedings of IEEE International Conference on Computer-Aided Design},
year = {1991},
pages = {510--513}
}
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Abstract
Boolean unification is an algorithm to obtain the general solution of a given Boolean equation. Since the general solution provides a way to represent complete don't care sets in a functional form, Boolean unification can be a powerful method when applied to logic synthesis. In this paper we present various applications of Boolean unification to combinational logic synthesis. Three topics of combinational logic synthesis: redesign, multi-level logic minimization and minimization of Boolean relations are discussed. All these problems can be uniformly formalized as Boolean unification problems. Experimental results are also reported. 1 Introduction Boolean Unification[9, 8] is a procedure to obtain the general solution of a given Boolean equation or formula. In the field of CAD for integrated circuit design, it has been applied to logic verification and test pattern generation [11, 4] combined with logic programming. In this paper we present various applications of Boolean unification...
