IDRA (IDeal Resource Allocation): Computing Ideal Speedups in Parallel Logic Programming
BibTeX
@MISC{Hermenegildo_idra(ideal,
author = {Fern'andez Carro Hermenegildo and M. J. Fern and Ez M. Carro M. Hermenegildo},
title = {IDRA (IDeal Resource Allocation): Computing Ideal Speedups in Parallel Logic Programming},
year = {}
}
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Abstract
. We present a technique to estimate accurate speedups for parallel logic programs with relative independence from characteristics of a given implementation or underlying parallel hardware. The proposed technique is based on gathering accurate data describing one execution at run--time, which is fed to a simulator. Alternative schedulings are then simulated and estimates computed for the corresponding speedups. A tool implementing the aforementioned techniques is presented, and its predictions are compared to the performance of real systems, showing good correlation. Keywords: Parallel Logic Programming; Simulation; Parallelism; Concurrency; Performance Evaluation. 1 Introduction In recent years a number of parallel implementations of logic programming languages, and, in particular, of Prolog, have been proposed (some examples are [HG91, AK90, SCWY90, She92, Lus90]). Relatively extensive studies have been performed regarding the performance of these systems. However, these studies g...
Keyphrases
parallel logic programming ideal resource allocation ideal speedup accurate speedup parallel implementation extensive study underlying parallel hardware alternative scheduling parallel logic program recent year run time good correlation relative independence accurate data real system performance evaluation aforementioned technique logic programming language corresponding speedup
