RRANN: A Hardware Implementation of the Backpropagation Algorithm Using Reconfigurable FPGAs (1994)
by
James G. Eldredge
,
Brad L. Hutchings
| Venue: | In IEEE World Conference on Computational Intelligence |
| Citations: | 14 - 2 self |
BibTeX
@INPROCEEDINGS{Eldredge94rrann:a,
author = {James G. Eldredge and Brad L. Hutchings},
title = {RRANN: A Hardware Implementation of the Backpropagation Algorithm Using Reconfigurable FPGAs},
booktitle = {In IEEE World Conference on Computational Intelligence},
year = {1994},
pages = {2097--2102}
}
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Abstract
This paper presents the Run-Time Reconfiguration Artificial Neural Network (RRANN). RRANN is a hardware implementation of the backpropagation algorithm that is extremely scalable and makes efficient use of FPGA resources. One key feature is RRANN's ability to exploit parallelism in all stages of the backpropagation algorithm including the stage where errors are propagated backward through the network.
