Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking (1996)
| Venue: | In Proceedings of the Formal Methods on Computer-Aided Design |
| Citations: | 23 - 7 self |
BibTeX
@INPROCEEDINGS{Chen96verificationof,
author = {Yirng-an Chen and Edmund Clarke and Pei-Hsin Ho and Yatin Hoskote and Timothy Kam and Manpreet Khaira and John O'Leary and Xudong Zhao},
title = {Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking},
booktitle = {In Proceedings of the Formal Methods on Computer-Aided Design},
year = {1996},
pages = {pp.},
publisher = {Springer-Verlag}
}
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Abstract
This paper presents the formal verification of all sub-circuits in a floating-point arithmetic unit (FPU) from an Intel microprocessor using a wordlevel model checker. This work represents the first large-scale application of word-level model checking techniques. The FPU can perform addition, subtraction, multiplication, square root, division, remainder, and rounding operations; verifying such a broad range of functionality required coupling the model checker with a number of other techniques, such as property decomposition, propertyspecific model extraction, and latch removal. We will illustrate our verification techniques using the Weitek WTL3170/3171 Sparc floating point coprocessor as an example. The principal contribution of this paper is a practical verification methodology explaining what techniques to apply (and where to apply them) when verifying floating-point arithmetic circuits. We have applied our methods to the floating-point unit of a state-of-the-art Intel microprocesso...
