## Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing (1999)

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Venue: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |

Citations: | 7 - 0 self |

### BibTeX

@ARTICLE{Cong99theoryand,

author = {Jason Cong and Lei He},

title = {Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing},

journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

year = {1999},

volume = {18},

pages = {406--420}

}

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### Abstract

In this paper we formulate three classes of optimization problems: the simple, monotonically constrained, and bounded Cong-He (CH)-programs. We reveal the dominance property under the local refinement (LR) operation for the simple CH-program, as well as the general dominance property under the pseudo-LR operation for the monotonically constrained CH-program and the extended-LR operation for the bounded CH-program. These properties enable a very efficient polynomial-time algorithm, using different types of LR operations to compute tight lower and upper bounds of the exact solution to any CH-program. We show that the algorithm is capable of solving many layout optimization problems in deep submicron iterative circuit and/or high-performance multichip module (MCM) and printed circuit board (PCB) designs. In particular, we apply the algorithm to the simultaneous transistor and interconnect sizing problem, and to the global interconnect sizing and spacing problem considering the coupling cap...

### Citations

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Citation Context ...but may be not true for the discrete sizing formulation and more general models for the interconnect capacitance and device delay. Our LR-based algorithm is similar to the coordinate descent approach =-=[24]-=- for the posynomial program. The approach iteratively optimizes the value for each variable (i.e., coordinate) while keeping the values for the rest of the variables fixed. 10 Because the local optimu... |

167 |
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Citation Context ...l program has the important property that the local optimum is unique, and therefore is also the global optimum. The posynomial program plays an important role in the device and wire sizing works. In =-=[21]-=-, the transistor sizing problem was first formulated as a posynomial program and solved by a sensitivity-based method. Later on, the posynomial program formulation was used for exact transistor sizing... |

150 |
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Citation Context ...yer and both top and down grounds (two layers away from the victim). We assume that wires in the basic geometric structure have same widths, then apply a numerical capacitance extraction tool FastCap =-=[13]-=- to solve the structure, using interconnect geometric parameters for the 0.18 m technology in NTRS, Table 22. 1 Fig. 2(a) depicts the unit-length ground capacitance between the victim and grounds, wit... |

106 | Optimal wire sizing and buffer insertion for low power and a generalized delay model - Lillis, Cheng, et al. - 1995 |

102 | Performance optimization of VLSI interconnect layout
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Citation Context ...DSM) designs [1]. Many optimization techniques have been proposed to reduce interconnect delay, including interconnect topology optimization, buffer insertion, and device and interconnect sizing (see =-=[2]-=- for a comprehensive survey). Manuscript received September 23, 1998. This work was supported in part by Defense Advanced Research Project Agency (DARPA) Electric Technology Office (ETO) under Contrac... |

90 | An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
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Citation Context ... the transistor sizing problem was first formulated as a posynomial program and solved by a sensitivity-based method. Later on, the posynomial program formulation was used for exact transistor sizing =-=[22]-=-, wire sizing [23] and simultaneous gate and wire sizing [9], and was solved by being transformed into the convex program. 9 Note that optimality of these solutions depends on the assumption that the ... |

67 | Interconnect design for deep submicron ICs
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Citation Context ... refinement, optimization methods, wire sizing, wire spacing. I. INTRODUCTION T he interconnect delay has become the dominant factor in determining circuit performance in deep submicron (DSM) designs =-=[1]-=-. Many optimization techniques have been proposed to reduce interconnect delay, including interconnect topology optimization, buffer insertion, and device and interconnect sizing (see [2] for a compre... |

62 |
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Citation Context ...s the same spacing but different wire widths, and each curve in (b) has the same center-to-edge spacing but different wire widths. The capacitance values are given for the unit-length wire. the model =-=[14]-=-. The resulting sizing problem, however, is no longer a posynomial program. It is unknown how far away the solution obtained by solving a posynomial program is from the exact solution under the voltag... |

53 | Optimal wiresizing under the distributed elmore delay model - Cong, Leung - 1993 |

50 | Simultaneous driver and wire sizing for performance and power optimization
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Citation Context ...ice and interconnect sizing problem in DSM designs. Several recent studies considered the simultaneous device and interconnect sizing problem. One class of algorithms minimizes the weighted delay. In =-=[3]-=-, the simultaneous driver and wire sizing problem was formulated to minimize the weighted delay between the source and a set of sinks for a single net. Procedures of device sizing and wire sizing are ... |

41 | Optimal wiresizing for interconnects with multiple sources
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Citation Context ... single net. Procedures of device sizing and wire sizing are alternately carried out, with device sizes computed by closedform formulas (via Maple) and wire widths computed by algorithms from [4] and =-=[5]-=-. In [6] and [7], the simultaneous transistor and interconnect sizing problem was studied to minimize the weighted delay for multiple paths (a path contains multiple nets). The local refinement operat... |

39 |
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Citation Context ...endations, we saved the name "bounded" for the type of CH-function defined in Definition 3, which was called the general CH-posynomial in [18]. CH-function is a subset of the posynomial. A p=-=osynomial [20]-=- is a function of a positive vector having the form with (2) where the exponents are real numbers and the coefficients are positive. For example, (3) is a simple CH-function as well as a posynomial. H... |

38 | Global interconnect sizing and spacing with consideration of coupling capacitance
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(Show Context)
Citation Context ...s no longer a posynomial program. It is unknown how far away the solution obtained by solving a posynomial program is from the exact solution under the voltage-ramp model. Two very recent works [15], =-=[16]-=- began to consider coupling capacitance for multiple nets. 2 Both allow variable but still assume that and are constants. Even though all these algorithms still use the simple model for either device ... |

33 |
A sequential quadratic programming approach to concurrent gate and wiring sizing
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(Show Context)
Citation Context ...as a convex quadratic program to find the lengths of wire segments for different wire widths. The other class of simultaneous device and interconnect sizing algorithms considers the maximum delay. In =-=[9]-=-, the simultaneous gate and wire sizing problem was formulated to minimize the area under the maximum-delay constraint for multiple paths. The problem is shown to be a posynomial program, and is trans... |

28 |
Fast performance-driven optimization for buffered clock trees based on lagrangian relaxation
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Citation Context .../99$10.00 �� 1999 IEEE CONG AND HE: THEORY AND ALGORITHM OF LOCAL-REFINEMENT-BASED OPTIMIZATION 407 TABLE I UNIT-SIZE EFFECTIVE-RESISTANCE FOR n- AND p-TRANSISTOR relaxation technique was proposed=-= in [11]-=- to optimally assign the weights for the sequence of weighted-delay minimizations. The simultaneous buffer and wire sizing problem was also solved [11]. However, most of these works assumed over-simpl... |

28 | Optimal wire and transistor sizing for circuits with non-tree topology
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(Show Context)
Citation Context ...ver, is no longer a posynomial program. It is unknown how far away the solution obtained by solving a posynomial program is from the exact solution under the voltage-ramp model. Two very recent works =-=[15]-=-, [16] began to consider coupling capacitance for multiple nets. 2 Both allow variable but still assume that and are constants. Even though all these algorithms still use the simple model for either d... |

19 | Analysis and justification of a simple, practical 2 1/2-d capacitance extraction methodology
- Cong, He, et al.
- 1997
(Show Context)
Citation Context ...ng formulation. B. Bound Computation for the Symmetric GISS Problem Our WS-bounded capacitance model is a table-based model simplified from the two and one-half dimensional (2-D) capacitance model in =-=[27]-=-. In this model, we first use the numerical capacitance extraction to solve the basic geometric structure with equal widths and spacings (see Fig. 1). We consider different width and spacing combinati... |

19 | Simultaneous buffer and wire sizing for performance and power optimization
- Cong, Koh, et al.
- 1996
(Show Context)
Citation Context ... to several problems, including the single-source and multisource wire sizing problems [4], [5], continuous wire sizing problem [19], and simultaneous driver/buffer and wire sizing problem [3], [11], =-=[28]-=-. Because these problems assume the simple models for the device delay and interconnect capacitance, they are all simple CH-program where the LR operation can be used for bound computations. Furthermo... |

18 |
A Sensitivity-Based Wiresizing Approach to Interconnect OPtimization of Lossy Transmission Line Topologies
- Xue, Kuh, et al.
- 1996
(Show Context)
Citation Context ...nce, we plan to develop methods computing the lower and upper bounds for , which may be more efficient than computing directly. The Elmore delay model is used in this paper. Several recent works [9], =-=[30]-=-, [31] have applied the higher-order delay model. We also plan to extend the LR-based algorithm to consider the higher-order delay model, or the table-based delay model as used in [32]. Note that the ... |

15 |
A Fast Algorithm for Optimal Wire-Sizing Under Elmore Delay Model
- Chen, Wong
- 1996
(Show Context)
Citation Context ...r many layout optimization problems in DSM designs. It unifies solutions to several problems, including the single-source and multisource wire sizing problems [4], [5], continuous wire sizing problem =-=[19]-=-, and simultaneous driver/buffer and wire sizing problem [3], [11], [28]. Because these problems assume the simple models for the device delay and interconnect capacitance, they are all simple CH-prog... |

14 | Wire sizing as a convex optimization problem: exploring the area-delay tradeo
- Sapatnekar
- 1996
(Show Context)
Citation Context ...zing problem was first formulated as a posynomial program and solved by a sensitivity-based method. Later on, the posynomial program formulation was used for exact transistor sizing [22], wire sizing =-=[23]-=- and simultaneous gate and wire sizing [9], and was solved by being transformed into the convex program. 9 Note that optimality of these solutions depends on the assumption that the local optimum is u... |

14 |
Simultaneous gate and interconnect sizing for circuit-level delay optimization
- Menezes, Pullela, et al.
- 1995
(Show Context)
Citation Context ...e plan to develop methods computing the lower and upper bounds for , which may be more efficient than computing directly. The Elmore delay model is used in this paper. Several recent works [9], [30], =-=[31]-=- have applied the higher-order delay model. We also plan to extend the LR-based algorithm to consider the higher-order delay model, or the table-based delay model as used in [32]. Note that the coupli... |

13 | A New Approach to Simultaneous Buffer Insertion and - Chu, Wong - 1997 |

12 | Greedy wire-sizing is linear time
- Chu, Wong
- 1998
(Show Context)
Citation Context ...ng the values for the rest of the variables fixed. 10 Because the local optimum is unique for the posynomial program regarding continuous variables, one may even start with an arbitrary solution (see =-=[25]-=-) rather than a lower or upper bound used in the LR-based algorithm. However, when the variables are of discrete values for the simple CH-program, or when the coefficients are not constants as in the ... |

11 | Table-lookup methods for improved performance-driven routing
- Lillis, Buch
- 1998
(Show Context)
Citation Context ...cent works [9], [30], [31] have applied the higher-order delay model. We also plan to extend the LR-based algorithm to consider the higher-order delay model, or the table-based delay model as used in =-=[32]-=-. Note that the coupling capacitance affects not only the interconnect delay, but also the signal integrity. Furthermore, the inductive effect becomes increasingly significant for global interconnects... |

7 | Theory and algorithm of local-refinement based optimization with application to device and interconnect sizing - Cong, He - 1999 |

4 |
A 12.7Mchip/s all-digital BPSK direct sequence spread-spectrum IF transceiver in 1.2m CMOS
- Chien, Yang, et al.
- 1994
(Show Context)
Citation Context ...:sTo illustrate the effectiveness of the STIS algorithm, we first compare the sizing solution obtained by our algorithm and the manual optimization applied to a spread spectrum IF transceiver chip in =-=[26]-=-. The design is under the 1.2- m twolayer metal SCMOS technology. There are two clock nets, dclk and clk; each uses a chain of four cascade drivers in the clock signal source and chains of four cascad... |

2 | efficient approach to simultaneous transistor and interconnect sizing - “An - 1996 |

1 |
User manual for TRIO—UCLA interconnect optimization package
- Cong, He, et al.
- 1998
(Show Context)
Citation Context ... 10 s to optimize the largest example in this paper. Solutions to the STIS and GISS problems, as well as other device and wire sizing problems [3]--[5], [28], have been integrated in the TRIO package =-=[29]-=-. Routines using the LR, PLR, ELR, and BLR operations are shared. Note that our bound-computation algorithm is applicable to any bounded model for the device delay and interconnect capacitance. The bo... |

1 | transistor and interconnect sizing based on the general dominance property - “Simultaneous - 1996 |

1 | efficient technique for device and interconnect optimization in deep submicron designs - “An - 1998 |