DMCA
Energy-Efficient Dual-Voltage Design Using Topological Constraints (2013)
BibTeX
@MISC{Electronics13energy-efficientdual-voltage,
author = {Low Power Electronics and Mridula Allani and Vishwani Agrawal},
title = {Energy-Efficient Dual-Voltage Design Using Topological Constraints},
year = {2013}
}
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Abstract
We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given a circuit and its nominal single supply voltage, we find a suitable value for a lower second supply voltage that is likely to give the best advantage in power reduction. Besides, using the critical path timing constraint and a linear-time gate slack calculation we also classify gates into three groups. All gates in Group 1 can be simultaneously assigned the lower voltage. Any gate in Group 2 can be assigned the lower voltage but then gate slacks must be recalculated because the group classifications may change. No gate in Group 3 can be assigned the lower voltage. A second step then assigns the lower voltage to the largest possible number of gates using the gate classifications and imposing a topological constraint, preventing any low voltage gate from feeding into a higher voltage gate, thus avoiding the use of level converters. SPICE simulation of dual-voltage ISCAS’85 benchmark circuits using the 90nm bulk CMOS PTM (predictive technology model) shows energy savings of up to 60 % with no increase in the original critical path delay and up to 70 % with relaxed critical path delay.
Keyphrases
low voltage gate bulk cmos ptm energy consumption nominal single supply voltage possible number gate classification second supply voltage critical path timing constraint relaxed critical path delay power reduction benchmark circuit group classification topological constraint level converter predictive technology model suitable value performance requirement new two-step procedure second step dual-voltage iscas spice simulation energy saving basic idea dual supply voltage digital design voltage gate linear-time gate slack calculation non-critical path original critical path delay
