Generation of Hardware Machine Models from Instruction Set Descriptions (1993)
| Venue: | in Proc. of the IEEE Workshop on VLSI Signal Processing |
| Citations: | 16 - 7 self |
BibTeX
@INPROCEEDINGS{Fauth93generationof,
author = {A. Fauth and M. Freericks and A. Knoll},
title = {Generation of Hardware Machine Models from Instruction Set Descriptions},
booktitle = {in Proc. of the IEEE Workshop on VLSI Signal Processing},
year = {1993},
pages = {242--250}
}
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Abstract
This paper describes how a modular machine description, which specifies the functionality and the binary representation of an instruction set, can be transformed into a hardware model. This model is built from few generic hardware entities (registers, memories, arithmetic/logic operators, selectors and connections) and may eventually serve as an input to high-level hardware synthesis tools. The transformation steps on the way from the machine description to the hardware model are explained by giving an example.
Citations
| 44 | The nML Machine Description Formalism - Freericks - 1993 |
| 27 | Tree-based mapping of algorithms to predefined structures - Marwedel - 1993 |
| 18 | Automated generation of DSP program development tools using a machine description formalism - Fauth, Knoll - 1993 |
| 10 | Translating Signal Flowcharts into Microcode for Custom Digital Signal Processors - Fauth, Knoll - 1993 |
| 9 | An Object-oriented Framework Supporting the Full High-level Synthesis Trajectory - Lanneer, Goossens, et al. - 1991 |
| 1 | Erstellung eines Werkzeugs zur automatischen Generierung eines Simulators aus einer abstrakten Maschinenbeschreibung - Lohr - 1992 |
| 1 | The Architectural Compiler Front End for CBC. Esprit 2260 - Hand - 1992 |
