A 3.3V Single-Poly CMOS Audio ADC Delta-Sigma Modulator with 98dB Peak SINAD and 105dB Peak SFDR (2000)
| Venue: | IEEE J. Solid-State Circuits |
| Citations: | 16 - 11 self |
BibTeX
@ARTICLE{Fogleman00a3.3v,
author = {Eric Fogleman and Ian Galton and William Huff and Henric Jensen and Student Member and Student Member and Henrik Jensen Member},
title = {A 3.3V Single-Poly CMOS Audio ADC Delta-Sigma Modulator with 98dB Peak SINAD and 105dB Peak SFDR},
journal = {IEEE J. Solid-State Circuits},
year = {2000},
volume = {35},
pages = {297--307}
}
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Abstract
This paper presents a second-order ## modulator for audio-band A#D conversion implemented in a 3.3V, 0.5#m, single-poly CMOS process using metal-metal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a low-complexity #rst-order mismatch-shaping 33-level DAC and a 33-level #ash ADC with digital common-mode rejection and dynamic element matching of comparator o#sets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS technology optimized for digital circuits. I. Introduction For mixed-signal ICs with high digital circuit content, single-poly CMOS optimized for digital circuits can provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of double-poly capacitors, thick-oxide transistors for 5V operation, or other analog process enhancements when analog circuits such as data converters make up only a small portion of the total die area. This ...
